Inventor

FAN JIEWEN

CN17 patents

⚠️ This page may combine multiple inventors who share the name “FAN JIEWEN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

FAN JIEWEN

HUANG RU

Method for testing density and location of gate dielectric layer trap of semiconductor device

High voltage-resistant lateral double-diffused transistor based on nanowire device

Fabrication method for surrounding gate silicon nanowire transistor with air as spacers

Method for fabricating surrounding-gate silicon nanowire transistor with air sidewalls

Field effect transistor with a vertical channel and fabrication method thereof

Method for fabricating silicon nanowire field effect transistor based on wet etching

Fabrication method of vertical silicon nanowire field effect transistor

Method for testing trap density of gate dielectric layer in semiconductor device having no substrate contact

Method for fabricating semiconductor nano circular ring

Programmable array of silicon nanowire field effect transistor and method for fabricating the same

UNIV BEIJING

Integration method for a vertical nanowire transistor

Method for fabricating ultra-fine nanowire

Method for fabricating FinFET with separated double gates on bulk silicon

Method of adjusting a threshold voltage of a multi-gate structure device

Method for fabricating multi-gate structure device with source and drain having quasi-SOI structure

Method for fabricating multiple layers of ultra narrow silicon wires

Method for fabricating quasi-SOI source/drain field effect transistor device