Inventor

PAUL SOMNATH

US45 patents

⚠️ This page may combine multiple inventors who share the name “PAUL SOMNATH”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

PAUL SOMNATH

CYPRESS SEMICONDUCTOR CORP

Logic for generating multicast/unicast address (es)

Logic for providing arbitration for synchronous dual-port memory

Scheduling store-forwarding of back-to-back multi-channel packet fragments

First-in-first-out (FIFO) memory for buffering packet fragments through use of read and write pointers incremented by a unit access and a fraction of the unit access

Multi-bit deskewing of bus signals using a training pattern

Method of maximizing bandwidth efficiency in a protocol processor

Method and apparatus for re-accessing a FIFO location

Configurable and memory architecture independent memory built-in self test

Configurable fast clock detection logic with programmable resolution

Architecture for implementing virtual multiqueue fifos

Logic for initializing the depth of the queue pointer memory

Low-latency interrupt handling during memory access delay periods in microprocessors

Low-latency DMA handling in pipelined processors

FIFO read interface protocol

Out-of-band look-ahead arbitration method and/or architecture

Fifo read interface protocol

Method and logic for storing and extracting in-band multicast port information stored along with the data in a single memory without memory read cycle overhead

Method and apparatus for collecting statistical information from a plurality of packet processing blocks

Method and apparatus for assembling non-aligned packet fragments over multiple cycles

FIFO memory system and method

Method and/or architecture for implementing queue expansion in multiqueue devices

Method and logic for initializing the forward-pointer memory during normal operation of the device as a background process

Multiple byte data path encoding/decoding device and method

Method and apparatus for the deletion of bytes when performing byte rate adaptation

INTEL CORP

Apparatuses, methods, and systems for stochastic memory circuits using magnetic tunnel junctions

Method and system of temporal-domain feature extraction for automatic speech recognition

Apparatuses, methods, and systems for stochastic memory circuits using magnetic tunnel junctions

Neuromorphic computing device, memory device, system, and method to maintain a spike history for neurons in a neuromorphic computing environment

Apparatus, video processing unit and method for clustering events in a content addressable memory

Post synaptic potential-based learning rule

Detecting keywords in audio using a spiking neural network

Concurrent compute and ECC for in-memory matrix vector operations

Ultra-deep compute static random access memory with high compute throughput and multi-directional data propagation

Techniques for multi-read and multi-write of memory circuit

Techniques for multi-read and multi-write of memory circuit

Technologies for memory management of neural networks with sparse connectivity

Hardware offload circuitry

Energy efficient memory array with optimized burst read and write data access

Hybrid compression scheme for efficient storage of synaptic weights in hardware neuromorphic cores

Techniques for resilient communication

Pre-synaptic learning using delayed causal updates

Flip-flop circuit with low-leakage transistors

BAUMBACH JASON

Transmission of a continuous datastream through a re-clocked frame-based transport network

QLOGIC CORP

Methods and systems for securing data stored at a storage area network

PAUL SOMNATH

Embedded resilient buffer