Inventor

AUGUSTINE CHARLES

US40 patents

⚠️ This page may combine multiple inventors who share the name “AUGUSTINE CHARLES”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

AUGUSTINE CHARLES

INTEL CORP

Bitcell state retention

Write operations in spin transfer torque memory

Apparatuses, methods, and systems for stochastic memory circuits using magnetic tunnel junctions

All-digital voltage monitor (ADVM) with single-cycle latency

Physically unclonable function circuit including memory elements

Physically unclonable function circuit using resistive memory device

Method and system of temporal-domain feature extraction for automatic speech recognition

Apparatuses, methods, and systems for stochastic memory circuits using magnetic tunnel junctions

All-digital voltage monitor (ADVM) with single-cycle latency

Apparatus to reduce retention failure in complementary resistive memory

Neuromorphic computing device, memory device, system, and method to maintain a spike history for neurons in a neuromorphic computing environment

Apparatus and method for detecting single flip-error in a complementary resistive memory

Apparatus to reduce retention failure in complementary resistive memory

Digital clamp for state retention

Bitcell state retention

Encryption code generation using spin-torque NANO-oscillators

Apparatus, video processing unit and method for clustering events in a content addressable memory

Post synaptic potential-based learning rule

Detecting keywords in audio using a spiking neural network

All-digital closed loop voltage generator

Concurrent compute and ECC for in-memory matrix vector operations

Ultra-deep compute static random access memory with high compute throughput and multi-directional data propagation

Techniques for multi-read and multi-write of memory circuit

Techniques for multi-read and multi-write of memory circuit

Technologies for memory management of neural networks with sparse connectivity

Distributed and scalable all-digital low dropout integrated voltage regulator

Calibrated biasing of sleep transistor in integrated circuits

Unified retention and wake-up clamp apparatus and method

SRAM with P-type access transistors and complementary field-effect transistor technology

Energy efficient memory array with optimized burst read and write data access

Hybrid compression scheme for efficient storage of synaptic weights in hardware neuromorphic cores

Apparatus and method for detecting single flip-error in a complementary resistive memory

Magnetic storage cell memory with back hop-prevention

Memory cell with retention using resistive memory

Magnetic storage cell memory with back hop-prevention

Low power retention flip-flop with level-sensitive scan circuitry

Pre-synaptic learning using delayed causal updates

Flip-flop circuit with low-leakage transistors

NAEIMI HELIA

Resistive memory write operation with merged reset

RAYCHOWDHURY ARIJIT

Digital clamp for state retention