Inventor

KHELLAH MUHAMMAD M

US102 patents

⚠️ This page may combine multiple inventors who share the name “KHELLAH MUHAMMAD M”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

KHELLAH MUHAMMAD M

INTEL CORP

Floating-body memory cell write

Purge-based floating body memory

OTP antifuse cell and cell array

Method and apparatus to clamp SRAM supply voltage

Apparatuses, methods, and systems for stochastic memory circuits using magnetic tunnel junctions

Graphics processor sub-domain voltage regulation

Memory having bit line with resistor(s) between memory cells

Memory with dynamically adjustable supply

2-transistor floating-body dram

Method and apparatus to clamp SRAM supply voltage

Reducing power consumption in integrated circuits

Dual gate oxide one time programmable (OTP) antifuse cell

Apparatus and method for programming a memory array

1P1N 2T gain cell

Floating-body dynamic random access memory and method of fabrication in tri-gate technology

Stable memory cell read

Method and apparatus for leakage compensation with full Vcc pre-charge

Method and apparatus for switched adaptive clocking

Memory circuit

Memory cell driver circuits

Two transistor gain cell, method, and system

Crosspoint memory array utilizing one time programmable antifuse cells

Apparatus and method for a one-phase write to a one-transistor memory cell array

Apparatuses, methods, and systems for stochastic memory circuits using magnetic tunnel junctions

SRAM with forward body biasing to improve read cell stability

Dual loop digital low drop regulator and current sharing control apparatus for distributable voltage regulators

Voltage level shifter circuit

Non volatile data storage through dielectric breakdown

Low power serial link bus architecture

Floating-body dynamic random access memory and method of fabrication in tri-gate technology

SRAM cell power reduction circuit

Majority voter apparatus, systems, and methods

Overvoltage detection apparatus, method, and system

Floating-body dynamic random access memory with purge line

Floating-body dynamic random access memory with purge line

SRAM bit-line reduction

Static random access memory having leakage reduction circuit

Skewed repeater bus

Graphics processor sub-domain voltage regulation

Low swing bitline for sensing arrays

Apparatus for reducing write minimum supply voltage for memory

Apparatus, video processing unit and method for clustering events in a content addressable memory

Post synaptic potential-based learning rule

KULKARNI JAYDEEP P

Methods and systems to selectively boost an operating voltage of, and controls to an 8T bit-cell array and/or other logic blocks

Apparatus for reducing write minimum supply voltage for memory

WILKERSON CHRISTOPHER

Disabling cache portions during low voltage operations

Disabling cache portions during low voltage operations

WU WEI

Method of correcting adjacent errors by using BCH-based error correction coding

WANG YIH

Memory cell with improved write margin

MEINERZHAGEN PASCAL A

Apparatus for dual purpose charge pump