Inventor

RYAN KEVIN J

US100 patents

⚠️ This page may combine multiple inventors who share the name “RYAN KEVIN J”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

RYAN KEVIN J

MICRON TECHNOLOGY INC

Method of timing calibration using slower data rate pattern

Packet-oriented synchronous DRAM interface supporting a plurality of orderings for data block transfers within a burst sequence

Plural pipelined packet-oriented memory systems having a unidirectional command and address bus and a bidirectional data bus

Method and apparatus for collision-free data transfers in a memory device with selectable data or address paths

Synchronous memory device with dual page and burst mode operations

Method for switching between modes of operation

RAM controller interface device for RAM compatibility (memory translator hub)

Method and apparatus for memory array compressed data testing

Memory having a plurality of external clock signal inputs

Apparatus and methods for optically-coupled memory systems

System latency levelization for read data

Dual mode DDR SDRAM/SGRAM

Method and apparatus for synchronous data transfers in a memory device with selectable data or address paths

Synchronous DRAM modules including multiple clock out signals for increasing processing speed

DRAM with intermediate storage cache and separate read and write I/O

Memory device with multiple internal banks and staggered command execution

Memory having a plurality of external clock signal inputs

Simplified clocked DRAM with a fast command input

Memory device with multiple internal banks and staggered command execution

Apparatus and methods for optically-coupled memory systems

Apparatus and methods for optically-coupled memory systems

Apparatus and methods for optically-coupled memory systems

DRAM with hidden refresh

Memory device interface

Synchronous DRAM with selectable internal prefetch size

Device and system for adjusting delay in a data path based on comparison of data from a latch and data from a register

Method and apparatus for synchronous data transfers in a memory device with selectable data or address paths

Double data rate synchronous memory with block-write

Method and apparatus for synchronous data transfers in a memory device with selectable data or address paths

Method for selecting one or a bank of memory devices

Write data masking for higher speed DRAMs

Full page increment/decrement burst for DDR SDRAM/SGRAM

DRAM with intermediate storage cache and separate read and write I/O

Method and system for hiding refreshes in a dynamic random access memory

Method and apparatus for synchronous data transfers in a memory device with selectable data or address paths

Memory having a plurality of external clock signal inputs

Asynchronously-accessible memory device with mode selection circuitry for burst or pipelined operation

Method for selecting one or a bank of memory devices

Method and apparatus for reading write-modified read data in memory device providing synchronous data transfers

Full page increment/decrement burst for DDR SDRAM/SGRAM

Full page increment/decrement burst for DDR SDRAM/SGRAM

Method and apparatus for synchronous data transfers in a memory device with lookahead logic for detecting latency intervals

Full page increment/decrement burst for DDR SDRAM/SGRAM

System and method for optimizing interconnections of memory devices in a multichip module

Apparatus and methods for optically-coupled memory systems

Method of timing calibration using slower data rate pattern

Apparatus and methods for optically-coupled memory systems

Memory device interface

ADVANCED MEMORY INTERNATIONAL

Memory system having synchronous-link DRAM (SLDRAM) devices and controller

US POSTAL SERVICE

Methods and systems for determining privacy requirements for an information resource