Inventor
VARADARAJAN RAVI
US10 patents
⚠️ This page may combine multiple inventors who share the name “VARADARAJAN RAVI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
CADENCE DESIGN SYSTEMS INC
6 patentsUS5838583ANov 17, 1998
Optimized placement and routing of datapaths
CADENCE DESIGN SYSTEMS INC312 citations98
US5604680AFeb 18, 1997
Virtual interface representation of hierarchical symbolic layouts
CADENCE DESIGN SYSTEMS INC106 citations97
US5381343AJan 10, 1995
Hier archical pitchmaking compaction method and system for integrated circuit design
CADENCE DESIGN SYSTEMS INC59 citations96
US5581474ADec 3, 1996
Identifying overconstraints using port abstraction graphs
CADENCE DESIGN SYSTEMS INC27 citations92
US5568396AOct 22, 1996
Identifying overconstraints using port abstraction graphs
CADENCE DESIGN SYSTEMS INC32 citations92
US5281558AJan 25, 1994
Cloning method and system for hierarchical compaction
CADENCE DESIGN SYSTEMS INC47 citations91
ATRENTA INC
4 patentsUS8839171B1Sep 16, 2014
Method of global design closure at top level and driving of downstream implementation flow
ATRENTA INC26 citations87
US7451427B2Nov 11, 2008
Bus representation for efficient physical synthesis of integrated circuit designs
ATRENTA INC7 citations72
US8782582B1Jul 15, 2014
Efficient method to analyze RTL structures that cause physical implementation issues based on rule checking and overlap analysis
ATRENTA INC4 citations66
US8732647B1May 20, 2014
Method for creating physical connections in 3D integrated circuits
ATRENTA INC4 citations64