Inventor

MANNING TROY A

US286 patents

⚠️ This page may combine multiple inventors who share the name “MANNING TROY A”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

MANNING TROY A

MICRON TECHNOLOGY INC

Apparatuses and methods for performing logical operations using sensing circuitry

Apparatuses and methods for performing compare operations using sensing circuitry

Method and apparatus for determining actual write latency and accurately aligning the start of data capture with the arrival of data at a memory device

Method and apparatus for bit-to-bit timing correction of a high speed memory bus

Antifuse method to repair columns in a prefetched output memory architecture

Method and apparatus for adjusting the timing of signals over fine and coarse ranges

Method and apparatus for compressed data testing of more than one memory array

Delay-locked loop with binary-coupled capacitor

Method and apparatus for generating an internal clock signal that is synchronized to an external clock signal

Multi-bank memory input/output line selection

Memory device with staggered data paths

Address transition detection on a synchronous design

Synchronous burst extended data out DRAM

Burst EDO memory device with maximized write cycle timing

DRAM having multiple column address strobe operation

Distributed write data drivers for burst access memories

Burst EDO memory device

Memory device balanced switching circuit and method of controlling an array of transfer gates for fast switching times

Method and system for accessing rows in multiple memory banks within an integrated circuit

Method of synchronizing read timing in a high speed memory system

Method and apparatus for resynchronizing a plurality of clock signals used to latch respective digital signals, and memory device using same

Method and apparatus for resynchronizing a plurality of clock signals used in latching respective digital signals applied to a packetized memory device

Memory device with dual timing and signal latching control

Method and apparatus for generating multi-phase clock signals, and circuitry, memory devices, and computer systems using same

Method and apparatus for transferring test data from a memory array

Method and apparatus for coupling signals between two circuits operating in different clock domains

Two step memory device command buffer apparatus and method and memory devices and computer systems using same

Address transition detection in a synchronous design

Method and apparatus for memory array compressed data testing

Burst EDO memory address counter

Distributed write data drivers for burst access memories

Counter control circuit in a burst memory

Burst EDO memory device with maximized write cycle timing

Burst EDO memory device address counter

Burst EDO memory device having pipelined output buffer

System powered with inter-coupled charge pumps

Method and apparatus for adaptively adjusting the timing of a clock signal used to latch digital signals, and memory device using same

Method and apparatus for adaptively adjusting the timing of a clock signal used to latch digital signals, and memory device using same

Burst EDO memory device

Method of synchronizing read timing in a high speed memory system

System latency levelization for read data

Distributed write data drivers for burst access memories

Memory device and method having data path with multiple prefetch I/O configurations

Methods and apparatus for reading memory device register data

Delay-locked loop with binary-coupled capacitor

Distributed write data drivers for burst access memories

Method and apparatus for bit-to-bit timing correction of a high speed memory bus

Method and apparatus for generating expect data from a captured bit pattern, and memory device using same

Method and apparatus for generating an internal clock signal that is synchronized to an external clock signal

ADVANCED MEMORY INTERNATIONAL

Memory system having synchronous-link DRAM (SLDRAM) devices and controller