Inventor
LIN WENHE
SG28 patents
⚠️ This page may combine multiple inventors who share the name “LIN WENHE”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
CHARTERED SEMICONDUCTOR MFG
20 patentsUS6475908B1Nov 5, 2002
Dual metal gate process: metals and their silicides
CHARTERED SEMICONDUCTOR MFG128 citations99
US6743291B2Jun 1, 2004
Method of fabricating a CMOS device with integrated super-steep retrograde twin wells using double selective epitaxial growth
CHARTERED SEMICONDUCTOR MFG125 citations98
US6664156B1Dec 16, 2003
Method for forming L-shaped spacers with precise width control
CHARTERED SEMICONDUCTOR MFG76 citations98
US6458695B1Oct 1, 2002
Methods to form dual metal gates by incorporating metals and their conductive oxides
CHARTERED SEMICONDUCTOR MFG83 citations98
US6750519B2Jun 15, 2004
Dual metal gate process: metals and their silicides
CHARTERED SEMICONDUCTOR MFG45 citations96
US6486080B2Nov 26, 2002
Method to form zirconium oxide and hafnium oxide for high dielectric constant materials
CHARTERED SEMICONDUCTOR MFG65 citations96
US7005716B2Feb 28, 2006
Dual metal gate process: metals and their silicides
CHARTERED SEMICONDUCTOR MFG25 citations93
US6677652B2Jan 13, 2004
Methods to form dual metal gates by incorporating metals and their conductive oxides
CHARTERED SEMICONDUCTOR MFG24 citations93
US7445978B2Nov 4, 2008
Method to remove spacer after salicidation to enhance contact etch stop liner stress on MOS
CHARTERED SEMICONDUCTOR MFG22 citations92
US6670248B1Dec 30, 2003
Triple gate oxide process with high-k gate dielectric
CHARTERED SEMICONDUCTOR MFG48 citations92
US6534388B1Mar 18, 2003
Method to reduce variation in LDD series resistance
CHARTERED SEMICONDUCTOR MFG37 citations92
US6403425B1Jun 11, 2002
Dual gate oxide process with reduced thermal distribution of thin-gate channel implant profiles due to thick-gate oxide
CHARTERED SEMICONDUCTOR MFG25 citations92
US6709912B1Mar 23, 2004
Dual Si-Ge polysilicon gate with different Ge concentrations for CMOS device optimization
CHARTERED SEMICONDUCTOR MFG53 citations90
US6891233B2May 10, 2005
Methods to form dual metal gates by incorporating metals and their conductive oxides
CHARTERED SEMICONDUCTOR MFG15 citations84
US6524910B1Feb 25, 2003
Method of forming dual thickness gate dielectric structures via use of silicon nitride layers
CHARTERED SEMICONDUCTOR MFG13 citations84
US7256084B2Aug 14, 2007
Composite stress spacer
CHARTERED SEMICONDUCTOR MFG12 citations83
US6835989B2Dec 28, 2004
Methods to form dual metal gates by incorporating metals and their conductive oxides
CHARTERED SEMICONDUCTOR MFG9 citations74
US7615427B2Nov 10, 2009
Spacer-less low-k dielectric processes
CHARTERED SEMICONDUCTOR MFG3 citations62
US7022625B2Apr 4, 2006
Method of fabricating a gate dielectric layer with reduced gate tunnelling current and reduced boron penetration
CHARTERED SEMICONDUCTOR MFG4 citations60
US7615433B2Nov 10, 2009
Double anneal with improved reliability for dual contact etch stop liner scheme
CHARTERED SEMICONDUCTOR MFG1 citations50