Inventor

BOWONDER ANUPAMA

US24 patents

⚠️ This page may combine multiple inventors who share the name “BOWONDER ANUPAMA”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

BOWONDER ANUPAMA

INTEL CORP

Fin smoothing and integrated circuit structures resulting therefrom

Fin smoothing and integrated circuit structures resulting therefrom

Integrated circuit structures having asymmetric source and drain structures

Buried etch-stop layer to help control transistor source/drain depth

Epitaxial oxide plug for strained transistors

Integrated circuit structures with source or drain dopant diffusion blocking layers

Fin shaping and integrated circuit structures resulting therefrom

Fin smoothing and integrated circuit structures resulting therefrom

Channel structures with sub-fin dopant diffusion blocking layers

Fin shaping and integrated circuit structures resulting therefrom

Epitaxial oxide plug for strained transistors

Channel structures with sub-fin dopant diffusion blocking layers

Semiconductor layer between source/drain regions and gate spacers

Reduced contact resistivity with PMOS germanium and silicon doped with boron gate all around transistors

Transistors with channel and sub-channel regions with distinct compositions and dimensions

Sub-fin leakage reduction for template strained materials

Sub-fin leakage reduction for template strained materials

Multiple strain states in epitaxial transistor channel through the incorporation of stress-relief defects within an underlying seed material

Source or drain structures with relatively high germanium content

Source or drain structures with contact etch stop layer

Techniques for forming dual-strain fins for co-integrated n-MOS and p-MOS devices

Self-aligned gate edge architecture with alternate channel material

UNIV CALIFORNIA

Tunneling transistor suitable for low voltage operation

HU CHENMING

Tunneling transistor suitable for low voltage operation