Inventor
CETEGEN EDVIN
US31 patents
⚠️ This page may combine multiple inventors who share the name “CETEGEN EDVIN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
27 patentsUS10192810B2Jan 29, 2019
Underfill material flow control for reduced die-to-die spacing in semiconductor packages
INTEL CORP13 citations83
US12261150B2Mar 25, 2025
Mold shelf package design and process flow for advanced package architectures
INTEL CORP1 citations74
US12087731B2Sep 10, 2024
No mold shelf package design and process flow for advanced package architectures
INTEL CORP1 citations72
US11901333B2Feb 13, 2024
No mold shelf package design and process flow for advanced package architectures
INTEL CORP1 citations72
US11464139B2Oct 4, 2022
Conformable heat sink interface with a high thermal conductivity
INTEL CORP3 citations71
US10290561B2May 14, 2019
Thermal interfaces for integrated circuit packages
INTEL CORP2 citations71
US12009271B2Jun 11, 2024
Protruding SN substrate features for epoxy flow control
INTEL CORP2 citations70
US11574851B2Feb 7, 2023
Coupled cooling fins in ultra-small systems
INTEL CORP3 citations70
US11551994B2Jan 10, 2023
Liquid metal TIM with STIM-like performance with no BSM and BGA compatible
INTEL CORP2 citations69
US11282717B2Mar 22, 2022
Micro-electronic package with substrate protrusion to facilitate dispense of underfill between a narrow die-to-die gap
INTEL CORP2 citations69
US12176268B2Dec 24, 2024
Open cavity bridge co-planar placement architectures and processes
INTEL CORP0 citations62
US11942393B2Mar 26, 2024
Substrate with thermal insulation
INTEL CORP0 citations62
US11735495B2Aug 22, 2023
Active package cooling structures using molded substrate packaging technology
INTEL CORP1 citations62
US11502008B2Nov 15, 2022
Dual strip backside metallization for improved alt-FLI plating, KOZ minimization, test enhancement and warpage control
INTEL CORP0 citations61
US11545407B2Jan 3, 2023
Thermal management solutions for integrated circuit packages
INTEL CORP0 citations60
US12362250B2Jul 15, 2025
Protruding SN substrate features for epoxy flow control
INTEL CORP0 citations59
US12068222B2Aug 20, 2024
Dummy die structures of a packaged integrated circuit device
INTEL CORP1 citations59
US11832419B2Nov 28, 2023
Full package vapor chamber with IHS
INTEL CORP0 citations59
US11791274B2Oct 17, 2023
Multichip semiconductor package including a bridge die disposed in a cavity having non-planar interconnects
INTEL CORP0 citations59
US11776821B2Oct 3, 2023
Micro-electronic package with substrate protrusion to facilitate dispense of underfill between a narrow die-to-die gap
INTEL CORP0 citations59
US11776864B2Oct 3, 2023
Corner guard for improved electroplated first level interconnect bump height range
INTEL CORP0 citations59
US11887962B2Jan 30, 2024
Microelectronic structures including bridges
INTEL CORP0 citations58
US11646274B2May 9, 2023
Multi-package assemblies having foam structures for warpage control
INTEL CORP0 citations58
US11935861B2Mar 19, 2024
Underfill flow management in electronic assemblies
INTEL CORP0 citations57
US11769753B2Sep 26, 2023
Thermally-optimized tunable stack in cavity package-on-package
INTEL CORP0 citations57
US12334453B2Jun 17, 2025
Soldered metallic reservoirs for enhanced transient and steady-state thermal performance
INTEL CORP0 citations49
US12002727B2Jun 4, 2024
Barrier structures for underfill containment
INTEL CORP0 citations44