Inventor

MUCHHERLA KISHORE K

US75 patents

⚠️ This page may combine multiple inventors who share the name “MUCHHERLA KISHORE K”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

MUCHHERLA KISHORE K

MICRON TECHNOLOGY INC

Memory devices and electronic systems having a hybrid cache including static and dynamic caches with single and multiple bits per cell, and related methods

Memory having a static cache and a dynamic cache

Garbage collection

Redundant array of independent NAND for a three-dimensional memory array

Memory having a static cache and a dynamic cache

Temperature related error management

Memory having a static cache and a dynamic cache

Threshold voltage margin analysis

Read voltage adjustment

Media management operations based on health characteristics of memory cells

Media management operations based on a ratio of valid data

Separate partition for buffer and snapshot memory

Partitions within snapshot memory for buffer and snapshot memory

Threshold voltage distribution adjustment for buffer

Operation of mixed mode blocks

Memory management

Memory having a static cache and a dynamic cache

Temperature related error management

Memory management

Operation of mixed mode blocks

Adaptive scan frequency for detecting errors in a memory system

Dynamic superblock construction

Data age and validity-based memory management

Write-once memory encoded data

Media management operations based on health characteristics of memory cells

Dynamic superblock construction

Media management operations based on a ratio of valid data

Data dispersion-based memory management

Memory sub-system logical block address remapping

Redundant array of independent NAND for a three-dimensional memory array

Valid translation unit count-based memory management

Data age and validity-based memory management

Data dispersion-based memory management

Memory sub-system logical block address remapping

Valid translation unit count-based memory management

Redundant array of independent NAND for a three-dimensional memory array

Memory sub-system write sequence track

Memory sub-system scan

Memory devices and systems including static and dynamic caches, and related methods

Memory device crossed matrix parity

Memory sub-system write sequence track

Read calibration based on ranges of program/erase cycles

Memory device crossed matrix parity

Separate partition for buffer and snapshot memory

Partitions within snapshot memory for buffer and snapshot memory

Operation of mixed mode blocks

Read voltage calibration for copyback operation

Read window based on program/erase cycles

Threshold voltage distribution adjustment for buffer

LODESTAR LICENSING GROUP LLC

Partitioned memory having error detection capability