Inventor

BINFET JEREMY

US46 patents

⚠️ This page may combine multiple inventors who share the name “BINFET JEREMY”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

BINFET JEREMY

MICRON TECHNOLOGY INC

Memory plane access management

Methods including establishing a negative body potential in a memory cell

In-field block retiring

Memory array reset read operation

Memory sub-system sanitization

Power architecture for non-volatile memory

Separate partition for buffer and snapshot memory

Partitions within snapshot memory for buffer and snapshot memory

Threshold voltage distribution adjustment for buffer

NAND page buffer based security operations

Power management across multiple packages of memory dies

NAND page buffer based security operations

Power management

Using duplicate data for improving error correction capability

Memory sub-system sanitization

Power management

Apparatus and methods for thermal management in a memory

Using duplicate data for improving error correction capability

Memory plane access management

Separate partition for buffer and snapshot memory

Partitions within snapshot memory for buffer and snapshot memory

Power architecture for non-volatile memory

Apparatus for establishing a negative body potential in a memory cell

Read voltage calibration for copyback operation

Threshold voltage distribution adjustment for buffer

Trims corresponding to logical unit quantity

Partitioned memory having error detection capability

Read voltage calibration for copyback operation

Separate trims for buffer and snapshot

Apparatus and methods including establishing a negative body potential in a memory cell

Multiple current quantization values for peak power management

Program command generation with dummy data generation at a memory device

Program command generation with dummy data generation at a memory device

Memory array reset read operation

Memory array reset read operation

Power management across multiple packages of memory dies

Bit error management in memory devices

Cryptographic block locking in a non-volatile memory device

Scheduled interrupts for peak power management token ring communication

Threshold voltage based on program/erase cycles

Peak power management self-check

Data management during a copyback operation

Apparatus and methods including establishing a negative body potential in a memory cell

Peak power management priority override

PARAT KRISHNA K

In-field block retiring

LODESTAR LICENSING GROUP LLC

Partitioned memory having error detection capability