Inventor · disambiguated record
Christopher Edward Koob
Also filed as: KOOB CHRISTOPHER · KOOB CHRISTOPHER E · KOOB CHRISTOPHER EDWARD
37 granted patents·7 pending applications·162 citations·filing 1998–2023
96Inventor score
Top patents by PatentIndex Score
44 records- 0190US8341353B2System and method to access a portion of a level two memory and a level one memoryVENKUMAHANTI SURESH K·Filed 2010·Granted Dec 25, 2012·15 cites·27 claims
- 0289US10169246B2Reducing metadata size in compressed memory systems of processor-based systemsQUALCOMM INC·Filed 2017·Granted Jan 1, 2019·9 cites·21 claims
- 0379US9785211B2Independent power collapse methodologyQUALCOMM INC·Filed 2015·Granted Oct 10, 2017·3 cites·30 claims
- 0478US10198362B2Reducing bandwidth consumption when performing free memory list cache maintenance in compressed memory schemes of processor-based systemsQUALCOMM INC·Filed 2017·Granted Feb 5, 2019·3 cites·19 claims
- 0578US8719503B2Configurable cache and method to configure sameKOOB CHRISTOPHER EDWARD·Filed 2012·Granted May 6, 2014·4 cites·20 claims
- 0677US9606818B2Systems and methods of executing multiple hypervisors using multiple sets of processorsQUALCOMM INC·Filed 2013·Granted Mar 28, 2017·4 cites·31 claims
- 0776US7584233B2System and method of counting leading zeros and counting leading ones in a digital signal processorQUALCOMM INC·Filed 2005·Granted Sep 1, 2009·8 cites·39 claims
- 0874US8266409B2Configurable cache and method to configure sameKOOB CHRISTOPHER EDWARD·Filed 2009·Granted Sep 11, 2012·5 cites·38 claims
- 0973US10114756B2Externally programmable memory management unitQUALCOMM INC·Filed 2013·Granted Oct 30, 2018·3 cites·35 claims
- 1073US6252600B1Computer graphics system with dual FIFO interfaceIBM·Filed 1998·Granted Jun 26, 2001·68 cites·31 claims
- 1172US7809783B2Booth multiplier with enhanced reduction tree circuitryQUALCOMM INC·Filed 2006·Granted Oct 5, 2010·6 cites·24 claims
- 1269US9239799B2Memory management unit directed access to system interfacesINGLE AJAY ANANT·Filed 2008·Granted Jan 19, 2016·4 cites·28 claims
- 1366US8656137B2Computer system with processor local coherency for virtualized input/outputKOOB CHRISTOPHER EDWARD·Filed 2011·Granted Feb 18, 2014·2 cites·23 claims
- 1464US10061698B2Reducing or avoiding buffering of evicted cache data from an uncompressed cache memory in a compression memory system when stalled write operations occurQUALCOMM INC·Filed 2017·Granted Aug 28, 2018·1 cites·22 claims
- 1564US9858201B2Selective translation lookaside buffer search and page faultQUALCOMM INC·Filed 2015·Granted Jan 2, 2018·1 cites·24 claims
- 1663US9678758B2Coprocessor for out-of-order loadsQUALCOMM INC·Filed 2014·Granted Jun 13, 2017·1 cites·19 claims
- 1763US9501332B2System and method to reset a lock indicationQUALCOMM INC·Filed 2012·Granted Nov 22, 2016·1 cites·23 claims
- 1862US10025711B2Hybrid write-through/write-back cache policy managers, and related systems and methodsSASSONE PETER G·Filed 2012·Granted Jul 17, 2018·2 cites·28 claims
- 1961US11663011B2System and method of VLIW instruction processing using reduced-width VLIW processorQUALCOMM INC·Filed 2020·Granted May 30, 2023·0 cites·20 claims
- 2058US7801164B2Two dimensional timeout table mechanism with optimized delay characteristicsAGERE SYSTEMS INC·Filed 2006·Granted Sep 21, 2010·1 cites·20 claims
- 2158US7797366B2Power-efficient sign extension for booth multiplication methods and systemsQUALCOMM INC·Filed 2006·Granted Sep 14, 2010·1 cites·24 claims
- 2257US8943293B2Configurable cache and method to configure sameQUALCOMM INC·Filed 2014·Granted Jan 27, 2015·0 cites·20 claims
- 2357US7313089B2Method and apparatus for switching between active and standby switch fabrics with no loss of dataAGERE SYSTEMS INC·Filed 2001·Granted Dec 25, 2007·5 cites·15 claims
- 2457US7111289B2Method for implementing dual link list structure to enable fast link-list pointer updatesAGERE SYSTEMS INC·Filed 2001·Granted Sep 19, 2006·5 cites·12 claims
- 2557US6801991B2Method and apparatus for buffer partitioning without loss of dataAGERE SYSTEMS INC·Filed 2001·Granted Oct 5, 2004·6 cites·21 claims
- 2655US10719325B2System and method of VLIW instruction processing using reduced-width VLIW processorQUALCOMM INC·Filed 2017·Granted Jul 21, 2020·0 cites·20 claims
- 2754US2024419963A1Power neural network-based workload distribution in distributed computing systemsQUALCOMM INC·Filed 2023·Application pending·0 cites
- 2853US6668313B2Memory system for increased bandwidthAGERE SYSTEMS INC·Filed 2001·Granted Dec 23, 2003·3 cites·15 claims
- 2952US8995207B2Data storage for voltage domain crossingsKOOB CHRISTOPHER EDWARD·Filed 2011·Granted Mar 31, 2015·1 cites·34 claims
- 3051US2025165143A1System and method for reducing memory footprint for data stored in a compressed memory subsystemQUALCOMM INC·Filed 2023·Application pending·0 cites
- 3150US2025156396A1Data integrity detectionQUALCOMM INC·Filed 2023·Application pending·0 cites
- 3249US8260990B2Selective preclusion of a bus access requestCODRESCU LUCIAN·Filed 2007·Granted Sep 4, 2012·0 cites·31 claims
- 3349US2011125987A1Dedicated Arithmetic Decoding InstructionQUALCOMM INC·Filed 2009·Application pending·0 cites
- 3448US12175280B2Memory transaction managementQUALCOMM INC·Filed 2021·Granted Dec 24, 2024·0 cites·28 claims
- 3548US9767025B2Write-only dataless state for maintaining cache coherencyKOOB CHRISTOPHER EDWARD·Filed 2012·Granted Sep 19, 2017·0 cites·36 claims
- 3646US10482021B2Priority-based storage and access of compressed memory lines in memory in a processor-based systemQUALCOMM INC·Filed 2016·Granted Nov 19, 2019·0 cites·28 claims
- 3746US9824013B2Per thread cacheline allocation mechanism in shared partitioned caches in multi-threaded processorsKOOB CHRISTOPHER EDWARD·Filed 2012·Granted Nov 21, 2017·0 cites·20 claims
- 3842US9658793B2Adaptive mode translation lookaside buffer search and access faultQUALCOMM INC·Filed 2015·Granted May 23, 2017·0 cites·32 claims
- 3942US2020250101A1System and method for intelligent tile-based memory bandwidth managementQUALCOMM INC·Filed 2019·Application pending·0 cites
- 4041US9142268B2Dual-voltage domain memory buffers, and related systems and methodsQUALCOMM INC·Filed 2012·Granted Sep 22, 2015·0 cites·24 claims
- 4141US8234319B2System and method of performing two's complement operations in a digital signal processorKRITHIVASAN SHANKAR·Filed 2005·Granted Jul 31, 2012·0 cites·33 claims
- 4239US2022113901A1Read optional and write optional commandsQUALCOMM INC·Filed 2020·Application pending·0 cites
- 4338US10102031B2Bandwidth/resource management for multithreaded processorsQUALCOMM INC·Filed 2015·Granted Oct 16, 2018·0 cites·21 claims
- 4437US2018173623A1Reducing or avoiding buffering of evicted cache data from an uncompressed cache memory in a compressed memory system to avoid stalling write operationsQUALCOMM INC·Filed 2016·Application pending·0 cites
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