Inventor
WATANABE YOSINORI
US15 patents
⚠️ This page may combine multiple inventors who share the name “WATANABE YOSINORI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
CADENCE DESIGN SYSTEMS INC
14 patentsUS7587687B2Sep 8, 2009
System and method for incremental synthesis
CADENCE DESIGN SYSTEMS INC23 citations92
US7363605B1Apr 22, 2008
Eliminating false positives in crosstalk noise analysis
CADENCE DESIGN SYSTEMS INC27 citations91
US10607039B1Mar 31, 2020
Constrained metric optimization of a system on chip
CADENCE DESIGN SYSTEMS INC15 citations82
US10133837B1Nov 20, 2018
Method and apparatus for converting real number modeling to synthesizable register-transfer level emulation in digital mixed signal environments
CADENCE DESIGN SYSTEMS INC10 citations79
US9524366B1Dec 20, 2016
Annotations to identify objects in design generated by high level synthesis (HLS)
CADENCE DESIGN SYSTEMS INC17 citations77
US7472361B2Dec 30, 2008
System and method for generating a plurality of models at different levels of abstraction from a single master model
CADENCE DESIGN SYSTEMS INC7 citations72
US10262095B1Apr 16, 2019
Conversion of real number modeling code to cycle-driven simulation interface code for circuit design in digital mixed signal environments
CADENCE DESIGN SYSTEMS INC5 citations71
US10262088B1Apr 16, 2019
Converting real number modeling code to cycle-driven simulation interface code for circuit design in digital mixed signal environments
CADENCE DESIGN SYSTEMS INC6 citations71
US10409939B1Sep 10, 2019
Statistical sensitivity analyzer
CADENCE DESIGN SYSTEMS INC4 citations70
US10423741B1Sep 24, 2019
Constrained metric verification analysis of a system on chip
CADENCE DESIGN SYSTEMS INC3 citations69
US11748539B1Sep 5, 2023
Converting analog variable delay in real number modeling code to cycle-driven simulation interface code
CADENCE DESIGN SYSTEMS INC1 citations61
US7673259B2Mar 2, 2010
System and method for synthesis reuse
CADENCE DESIGN SYSTEMS INC1 citations51
US10140202B1Nov 27, 2018
Source code annotation for a system on chip
CADENCE DESIGN SYSTEMS INC1 citations49
US11868241B1Jan 9, 2024
Method and system for optimizing a verification test regression
CADENCE DESIGN SYSTEMS INC0 citations48