Inventor
RAHUT ANIRBAN
US24 patents
⚠️ This page may combine multiple inventors who share the name “RAHUT ANIRBAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
XILINX INC
16 patentsUS7430728B1Sep 30, 2008
Method and apparatus for selecting programmable interconnects to reduce clock skew
XILINX INC28 citations92
US6952813B1Oct 4, 2005
Method and apparatus for selecting programmable interconnects to reduce clock skew
XILINX INC20 citations92
US6766504B1Jul 20, 2004
Interconnect routing using logic levels
XILINX INC26 citations92
US8010923B1Aug 30, 2011
Latch based optimization during implementation of circuit designs for programmable logic devices
XILINX INC7 citations84
US7051312B1May 23, 2006
Upper-bound calculation for placed circuit design performance
XILINX INC11 citations84
US7389485B1Jun 17, 2008
Methods of routing low-power designs in programmable logic devices having heterogeneous routing architectures
XILINX INC16 citations83
US7424697B1Sep 9, 2008
Assigning inputs of look-up tables to improve a design implementation in a programmable logic device
XILINX INC13 citations82
US7904860B1Mar 8, 2011
Method and apparatus for selecting programmable interconnects to reduce clock skew
XILINX INC5 citations73
US7306977B1Dec 11, 2007
Method and apparatus for facilitating signal routing within a programmable logic device
XILINX INC7 citations73
US8015535B1Sep 6, 2011
Run-time efficient methods for routing large multi-fanout nets
XILINX INC2 citations63
US7620923B1Nov 17, 2009
Run-time efficient methods for routing large multi-fanout nets
XILINX INC2 citations63
US7376926B1May 20, 2008
Run-time efficient methods for routing large multi-fanout nets
XILINX INC1 citations63
US7797665B1Sep 14, 2010
Patterns for routing nets in a programmable logic device
XILINX INC3 citations62
US7725868B1May 25, 2010
Method and apparatus for facilitating signal routing within a programmable logic device
XILINX INC3 citations62
US7076758B1Jul 11, 2006
Using router feedback for placement improvements for logic design
XILINX INC6 citations62
US7735039B1Jun 8, 2010
Methods of estimating net delays in tile-based PLD architectures
XILINX INC6 citations60
SPLUNK INC
7 patentsUS9256501B1Feb 9, 2016
High availability scheduler for scheduling map-reduce searches
SPLUNK INC33 citations97
US9047246B1Jun 2, 2015
High availability scheduler
SPLUNK INC40 citations97
US9983954B2May 29, 2018
High availability scheduler for scheduling searches of time stamped events
SPLUNK INC2 citations73
US12282497B1Apr 22, 2025
Search result replication management in a search head cluster
SPLUNK INC0 citations62
US11704341B2Jul 18, 2023
Search result replication management in a search head cluster
SPLUNK INC0 citations62
US10698777B2Jun 30, 2020
High availability scheduler for scheduling map-reduce searches based on a leader state
SPLUNK INC0 citations52
US10133806B2Nov 20, 2018
Search result replication in a search head cluster
SPLUNK INC0 citations51