Inventor
SINGH BHUPENDER
US19 patents
⚠️ This page may combine multiple inventors who share the name “SINGH BHUPENDER”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
12 patentsUS11282773B2Mar 22, 2022
Enlarged conductive pad structures for enhanced chip bond assembly yield
IBM2 citations72
US11410894B2Aug 9, 2022
Polygon integrated circuit (IC) packaging
IBM1 citations62
US11211262B2Dec 28, 2021
Electronic apparatus having inter-chip stiffener
IBM0 citations62
US11756930B2Sep 12, 2023
High bandwidth module
IBM0 citations60
US11201136B2Dec 14, 2021
High bandwidth module
IBM0 citations60
US11521952B2Dec 6, 2022
Spacer for die-to-die communication in an integrated circuit and method for fabricating the same
IBM0 citations59
US11031373B2Jun 8, 2021
Spacer for die-to-die communication in an integrated circuit
IBM1 citations59
US11694992B2Jul 4, 2023
Near tier decoupling capacitors
IBM0 citations57
US11004614B2May 11, 2021
Stacked capacitors for use in integrated circuit modules and the like
IBM0 citations51
US11404365B2Aug 2, 2022
Direct attachment of capacitors to flip chip dies
IBM0 citations50
US11393759B2Jul 19, 2022
Alignment carrier for interconnect bridge assembly
IBM0 citations48
US11031343B2Jun 8, 2021
Fins for enhanced die communication
IBM0 citations48
ST MICROELECTRONICS INT NV
5 patentsUS11195576B2Dec 7, 2021
Robust adaptive method and circuit for controlling a timing window for enabling operation of sense amplifier
ST MICROELECTRONICS INT NV0 citations51
US12584961B2Mar 24, 2026
Built-in self test circuit for segmented static random access memory (SRAM) array input/output
ST MICROELECTRONICS INT NV0 citations50
US12437825B2Oct 7, 2025
At-speed transition fault testing for a multi-port and multi-clock memory
ST MICROELECTRONICS INT NV0 citations50
US12353341B2Jul 8, 2025
Tuning of read/write cycle time delay for a memory circuit dependent on operational mode selection
ST MICROELECTRONICS INT NV0 citations50
US12170120B2Dec 17, 2024
Built-in self test circuit for segmented static random access memory (SRAM) array input/output
ST MICROELECTRONICS INT NV0 citations50