Inventor
BRADFORD DENNIS R
US25 patents
⚠️ This page may combine multiple inventors who share the name “BRADFORD DENNIS R”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
23 patentsUS10146535B2Dec 4, 2018
Systems, apparatuses, and methods for chained fused multiply add
INTEL CORP23 citations93
US11693691B2Jul 4, 2023
Systems, methods, and apparatuses for heterogeneous computing
INTEL CORP4 citations85
US10268539B2Apr 23, 2019
Apparatus and method for multi-bit error detection and correction
INTEL CORP7 citations84
US10133577B2Nov 20, 2018
Vector mask driven clock gating for power efficiency of a processor
INTEL CORP8 citations84
US11487541B2Nov 1, 2022
Systems, apparatuses, and methods for chained fused multiply add
INTEL CORP4 citations83
US11416281B2Aug 16, 2022
Systems, methods, and apparatuses for heterogeneous computing
INTEL CORP4 citations83
US11093277B2Aug 17, 2021
Systems, methods, and apparatuses for heterogeneous computing
INTEL CORP6 citations83
US9513917B2Dec 6, 2016
Vector friendly instruction format and execution thereof
INTEL CORP10 citations82
US12135981B2Nov 5, 2024
Systems, methods, and apparatuses for heterogeneous computing
INTEL CORP1 citations72
US10853065B2Dec 1, 2020
Systems, apparatuses, and methods for chained fused multiply add
INTEL CORP3 citations72
US12073214B2Aug 27, 2024
Systems, apparatuses, and methods for chained fused multiply add
INTEL CORP0 citations62
US9152382B2Oct 6, 2015
Reducing power consumption in a fused multiply-add (FMA) unit responsive to input data values
INTEL CORP3 citations62
US12086594B2Sep 10, 2024
Vector friendly instruction format and execution thereof
INTEL CORP0 citations60
US11740904B2Aug 29, 2023
Vector friendly instruction format and execution thereof
INTEL CORP0 citations60
US11210096B2Dec 28, 2021
Vector friendly instruction format and execution thereof
INTEL CORP0 citations60
US10719320B2Jul 21, 2020
Power noise injection to control rate of change of current
INTEL CORP0 citations51
US9785436B2Oct 10, 2017
Apparatus and method for efficient gather and scatter operations
INTEL CORP1 citations51
US10795680B2Oct 6, 2020
Vector friendly instruction format and execution thereof
INTEL CORP0 citations50
US9606847B2Mar 28, 2017
Enabling error detecting and reporting in machine check architecture
INTEL CORP0 citations45
US9696992B2Jul 4, 2017
Apparatus and method for performing a check to optimize instruction flow
INTEL CORP0 citations44
US10423421B2Sep 24, 2019
Opportunistic utilization of redundant ALU
INTEL CORP0 citations41
US9842046B2Dec 12, 2017
Processing memory access instructions that have duplicate memory indices
INTEL CORP0 citations41
US9804842B2Oct 31, 2017
Method and apparatus for efficiently managing architectural register state of a processor
INTEL CORP0 citations38