Inventor
LE VAILLANT YVES MATTHIEU
FR10 patents
Patents
10 patentsUS7187162B2Mar 6, 2007
Tools and methods for disuniting semiconductor wafers
SOITEC SILICON ON INSULATOR32 citations92
US7740735B2Jun 22, 2010
Tools and methods for disuniting semiconductor wafers
SOITEC SILICON ON INSULATOR11 citations83
US7256075B2Aug 14, 2007
Recycling of a wafer comprising a multi-layer structure after taking-off a thin layer
SOITEC SILICON ON INSULATOR20 citations83
US7981768B2Jul 19, 2011
Method for transferring an epitaxial layer
SOITEC SILICON ON INSULATOR5 citations61
US7887936B2Feb 15, 2011
Substrate with determinate thermal expansion coefficient
SOITEC SILICON ON INSULATOR2 citations61
US7473620B2Jan 6, 2009
Process for adjusting the strain on the surface or inside a substrate made of a semiconductor material
SOITEC SILICON ON INSULATOR3 citations61
US7465646B2Dec 16, 2008
Methods for fabricating a wafer structure having a strained silicon utility layer
SOITEC SILICON ON INSULATOR4 citations61
US7439160B2Oct 21, 2008
Methods for producing a semiconductor entity
SOITEC SILICON ON INSULATOR6 citations59
US7176554B2Feb 13, 2007
Methods for producing a semiconductor entity
SOITEC SILICON ON INSULATOR1 citations48
US9240343B2Jan 19, 2016
Method for modifying an initial stress state of an active layer to a final stress state
SOITEC SILICON ON INSULATOR0 citations35