Inventor

GAU TSAI-SHENG

TW126 patents

⚠️ This page may combine multiple inventors who share the name “GAU TSAI-SHENG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

GAU TSAI-SHENG

TAIWAN SEMICONDUCTOR MFG

Spacer etching process for integrated circuit design

Apparatus and method for immersion lithography

Layout generation and optimization to improve photolithographic performance

Lithography using high selectivity spacers for pitch reduction

Method of merging color sets of layout

Self-alignment for using two or more layers and methods of forming same

Method for integrated circuit patterning

Method for improving the critical dimension uniformity of patterned features on wafers

Dissection splitting with optical proximity correction and mask rule check enforcement

Systems and methods for a sequential spacer scheme

Mechanisms for forming patterns using multiple lithography processes

Method of patterning a feature of a semiconductor device

Method for metal correlated via split for double patterning

System and method for direct writing to a wafer

Immersion optical projection system

Method and system for wafer inspection

Method and system for a pattern layout split

Method and system for improving accuracy of critical dimension metrology

Method and system for patterning alignment marks on a transparent substrate

Complementary replacement of material

Method of defining forbidden pitches for a lithography exposure tool

Immersion lithography system with wafer sealing mechanisms

Level adjustment systems and adjustable pin chuck thereof

Wafer repair method using direct-writing

Geometric compensation method for charged particle beam irradiation

TAIWAN SEMICONDUCTOR MFG CO LTD

Lithography using high selectivity spacers for pitch reduction

Method of fabricating semiconductor device with reduced trench distortions

Directional patterning methods

Lithography using high selectivity spacers for pitch reduction

Via connection to a partially filled trench

Methods for integrated circuit design and fabrication

Pellicle assembly and method of making same

Mechanisms for forming patterns using multiple lithography processes

Via connection to a partially filled trench

Methods for integrated circuit design and fabrication

Methods for generating a mandrel mask

Mechanisms for forming patterns using multiple lithography processes

Method of fabricating semiconductor device with reduced trench distortions

Lithographic technique incorporating varied pattern materials

Mandrel spacer patterning in multi-pitch integrated circuit manufacturing

Mechanisms for forming patterns using multiple lithography processes

WANG CHIEN-WEI

Patterning process and chemical amplified photoresist with a photodegradable base

Patterning process and photoresist with a photodegradable base

IND TECH RES INST

Illumination aperture filter design using superposition

Elimination of proximity effect in photoresist

CHEN YEN-LIANG

System and method for alignment in semiconductor device fabrication

CHEN PI-TSUNG

Decomposing integrated circuit layout

LIU GEORGE

Intensity selective exposure photomask

CHEN LI-JUI

In-line particle detection for immersion lithography

HUANG TE-CHIH

Measurement of overlay offset in semiconductor processing