Inventor
DREIBELBIS BRIAN M
US10 patents
⚠️ This page may combine multiple inventors who share the name “DREIBELBIS BRIAN M”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
BUCK NATHAN C
5 patentsUS8468483B2Jun 18, 2013
Method, system and program storage device for performing a parameterized statistical static timing analysis (SSTA) of an integrated circuit taking into account setup and hold margin interdependence
BUCK NATHAN C9 citations83
US8141012B2Mar 20, 2012
Timing closure on multiple selective corners in a single statistical timing run
BUCK NATHAN C18 citations83
US8656207B2Feb 18, 2014
Method for modeling variation in a feedback loop of a phase-locked loop
BUCK NATHAN C5 citations72
US9858368B2Jan 2, 2018
Integrating manufacturing feedback into integrated circuit structure design
BUCK NATHAN C3 citations70
US8768679B2Jul 1, 2014
System and method for efficient modeling of NPskew effects on static timing tests
BUCK NATHAN C5 citations70
IBM
4 patentsUS10970448B2Apr 6, 2021
Partial parameters and projection thereof included within statistical timing analysis
IBM0 citations62
US8056035B2Nov 8, 2011
Method and system for analyzing cross-talk coupling noise events in block-based statistical static timing
IBM5 citations62
US10489540B2Nov 26, 2019
Integrating manufacturing feedback into integrated circuit structure design
IBM0 citations52
US10394982B2Aug 27, 2019
Partial parameters and projection thereof included within statistical timing analysis
IBM0 citations51