Inventor

BEAUMONT-SMITH ANDREW J

US24 patents

⚠️ This page may combine multiple inventors who share the name “BEAUMONT-SMITH ANDREW J”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

BEAUMONT-SMITH ANDREW J

APPLE INC

Combining write buffer with dynamically adjustable flush metrics

Computation engine with extract instructions to minimize memory access

Coprocessor context priority

Coprocessors with bypass optimization, variable grid architecture, and fused vector operations

Coprocessor synchronizing instruction suppression

Coprocessor prefetcher

Processor employing split scheduler in which near, low latency operation dependencies are tracked separate from other operation dependencies

Debug trace of cache memory requests

Debug trace of cache memory requests

Coprocessors with bypass optimization, variable grid architecture, and fused vector operations

Coprocessor context priority

Coprocessors with bypass optimization, variable grid architecture, and fused vector operations

Coprocessor synchronizing instruction suppression

Coprocessor prefetcher

Coprocessor register renaming using registers associated with an inactive context to store results from an active context

Combining write buffer with dynamically adjustable flush metrics

Coprocessor with distributed register

BEAUMONT-SMITH ANDREW J

Store hit load predictor

Indirect branch target predictor that prevents speculation if mispredict is expected

Preventing update training of first predictor with mismatching second predictor for branch instructions with alternating pattern hysteresis

Processor employing split scheduler in which near, low latency operation dependencies are tracked separate from other operation dependencies

MURRAY DANIEL C

Instruction type issue throttling upon reaching threshold by adjusting counter increment amount for issued cycle and decrement amount for not issued cycle

HEWLETT PACKARD DEVELOPMENT CO

Method and system of a microprocessor subtraction-division floating point divider

GUNNA RAMESH B

Maintaining the integrity of an execution return address stack