Inventor

GUNNA RAMESH

US25 patents

⚠️ This page may combine multiple inventors who share the name “GUNNA RAMESH”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

GUNNA RAMESH

APPLE INC

Non-blocking address switch with shallow per agent queues

Converting victim writeback to a fill

L1 cache flush when processor is entering low power mode

Combining write buffer with dynamically adjustable flush metrics

Retry mechanism

R and C bit update handling

Non-blocking address switch with shallow per agent queues

Replay reduction for power saving

Latency reduction for cache coherent bus-based cache

Latency reduction for cache coherent bus-based cache

Latency reduction for cache coherent bus-based cache

Converting victim writeback to a fill

Retry mechanism

Data cache block zero implementation

GUNNA RAMESH

Store handling in a processor

Store handling in a processor

Data cache block zero implementation

Converting victim writeback to a fill

PA SEMI INC

Non-blocking address switch with shallow per agent queues

Combined buffer for snoop, store merging, load miss, and writeback operations

Retry mechanism in cache coherent communication among agents

BEAUMONT-SMITH ANDREW J

Indirect branch target predictor that prevents speculation if mispredict is expected

KELLER JAMES B

L1 flush mechanism to flush cache for power down and handle coherence during flush and/or after power down

PAN JESSE

R and C bit update handling

CHANG PO-YUNG

Replay reduction for power saving