Inventor

GANFIELD PAUL ALLEN

US27 patents

⚠️ This page may combine multiple inventors who share the name “GANFIELD PAUL ALLEN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

GANFIELD PAUL ALLEN

IBM

Data processing system, circuit arrangement and program product including multi-path scan interface and methods thereof

Boundary scan latch configuration for generalized scan designs

System and method for using LBIST to find critical paths in functional logic

System and method for minimizing simultaneous switching during scan-based testing

Method and apparatus for generating a mask value and command for extreme data rate memories utilizing error correction codes

Apparatus and method to change a processor clock frequency

Data strobe signals (DQS) for high speed dynamic random access memories (DRAMs)

SRAM that can be clocked on either clock phase

Separate handling of read and write of read-modify-write

Memory controller operating in a system with a variable system clock

Method and apparatus for handling variable data word widths and array depths in a serial shared abist scheme

Low-latency, high-availability and high-speed SerDes interface having multiple synchronization modes

Method and apparatus for implementing packet work area accesses and buffer sharing

Managing write-to-read turnarounds in an early read after write memory system

Reuse of functional data buffers for pattern buffers in XDR DRAM

Method, apparatus, and computer program product for implementing enhanced circular queue using loop counts

Memory controller operating in a system with a variable system clock

Separate handling of read and write of read-modify-write

Separate handling of read and write of read-modify-write

Low-latency deserializer having fine granularity and defective-lane compensation

Reuse of functional data buffers for pattern buffers in XDR DRAM

Managing write-to-read turnarounds in an early read after write memory system

Method and apparatus for managing write-to-read turnarounds in an early read after write memory system

Flexible sub-column to sub-row mapping for sub-page activation in XDR™ DRAMs

Method, apparatus, and computer program product for implementing packet ordering

Method and apparatus for implementing packet command instructions for network processing

BELLOWS MARK DAVID

Memory controller to utilize DRAM write buffers