Inventor
AKAVARAM SANTHOSH REDDY
IN25 patents
Patents
25 patentsUS12164448B2Dec 10, 2024
Mechanism to reduce exit latency for deeper power saving modes L2 in PCIe
QUALCOMM INC2 citations71
US12079061B2Sep 3, 2024
Power management for peripheral component interconnect
QUALCOMM INC1 citations60
US12517837B2Jan 6, 2026
Logical to physical lookup table update in a flash memory system
QUALCOMM INC0 citations59
US12461670B2Nov 4, 2025
Enhanced power management of flash memory device
QUALCOMM INC0 citations59
US12455828B2Oct 28, 2025
Host management of flash memory with shared write buffer
QUALCOMM INC0 citations59
US12197775B2Jan 14, 2025
Memory devices write buffer management
QUALCOMM INC0 citations59
US12153527B2Nov 26, 2024
Data rate increase for faulty lane recovery in multiple lane data links
QUALCOMM INC0 citations59
US12373359B2Jul 29, 2025
Mechanism to enhance PCIe generation switching
QUALCOMM INC0 citations58
US12332825B2Jun 17, 2025
Apparatus and method for configuring a interconnect link between chiplets
QUALCOMM INC1 citations58
US12056364B1Aug 6, 2024
Write buffer and logical unit management in a data storage device
QUALCOMM INC0 citations58
US12430199B2Sep 30, 2025
Flow control between peripheral component interconnect express devices
QUALCOMM INC0 citations56
US12282392B2Apr 22, 2025
Interconnects between chiplets and related link initialization protocols
QUALCOMM INC0 citations56
US12517667B2Jan 6, 2026
Host management of write buffer size for flash memory
QUALCOMM INC0 citations55
US12174757B1Dec 24, 2024
Apparatus and methods for reducing latencies associated with link state transitions within die interconnect architectures
QUALCOMM INC1 citations55
US12393479B1Aug 19, 2025
Exception event handling in flash memory system
QUALCOMM INC0 citations54
US11934335B2Mar 19, 2024
Power management for peripheral component interconnect
QUALCOMM INC0 citations50
US12461859B2Nov 4, 2025
Interrupting memory access during background operations on a memory device
QUALCOMM INC0 citations49
US12399853B2Aug 26, 2025
Mechanism to improve link initialization time
QUALCOMM INC0 citations49
US12271303B2Apr 8, 2025
System and method for updating memory tables
QUALCOMM INC0 citations49
US12019577B2Jun 25, 2024
Latency reduction for link speed switching in multiple lane data links
QUALCOMM INC0 citations49
US12430280B2Sep 30, 2025
Mechanism to improve the reliability of sideband in chiplets
QUALCOMM INC0 citations48
US12417023B2Sep 16, 2025
Host device caching of flash memory address mappings
QUALCOMM INC0 citations47
US12481453B2Nov 25, 2025
Unmapping a write buffer portion for access during a write to a memory device
QUALCOMM INC0 citations46
US12461822B2Nov 4, 2025
Mechanism to enhance link bandwidth in interconnects
QUALCOMM INC0 citations46
US12462032B2Nov 4, 2025
Systems and methods for improving security in universal flash devices regarding purge operations
QUALCOMM INC0 citations43