Inventor

KOWASHI EIICHI

JP47 patents

⚠️ This page may combine multiple inventors who share the name “KOWASHI EIICHI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

KOWASHI EIICHI

INTEL CORP

Method for performing multiply-add operations on packed data

Method and apparatus for performing multiply-subtract operations on packed data

Method and apparatus for performing multiply-add operations on packed data

Method and apparatus for multiplying and accumulating data samples and complex coefficients

Method and apparatus for multiplying and accumulating complex numbers in a digital filter

Method and apparatus for storing complex numbers to allow for efficient complex multiplication operations and performing such complex multiplication operations

Method of sorting numbers to obtain maxima/minima values with ordering

Method and apparatus for executing two types of instructions that specify registers of a shared logical register file in a stack and a non-stack referenced manner

Apparatus for performing multiply-add operations on packed data

Apparatus for performing multiply-add operations on packed data

Method for executing different sets of instructions that cause a processor to perform different data type operations on different physical registers files that logically appear to software as a single aliased register file

Method and apparatus for performing multiply and accumulate operations on packed data

Method and apparatus for multiplying and accumulating complex numbers in a digital filter

Method for executing instructions that operate on different data types stored in the same single logical register file

System for signal processing using multiply-add operations

Computer system for performing complex digital filters

Emptying packed data state during execution of packed data instructions

Computer implemented method for transferring packed data between register files and memory

Executing different instructions that cause different data type operations to be performed on single logical register file

Simd with selective idling of individual processors based on stored conditional flags, and with consensus among all flags used for conditional branching

Single-instruction multiple-data processor having dual-ported local memory architecture for simultaneous data transmission on local memory ports and global port

Method and apparatus for multiplying and accumulating complex numbers in a digital filter

Computer system performing a two-dimensional rotation of packed data representing multimedia information

System for configuring memory space for storing single decoder table, reconfiguring same space for storing plurality of decoder tables, and selecting one configuration based on encoding scheme

Method for performing complex fast fourier transforms (FFT&#39;s)

Processor for performing multiply-add operations on packed data

Method and apparatus for performing multiply-add operations on packed data

Processor with instructions that operate on different data types stored in the same single logical register file

Emptying packed data state during execution of packed data instructions

Method of sorting numbers to obtain maxima/minima values with ordering

Method of sorting signed numbers and solving absolute differences using packed instructions

Method for performing multiply-substrate operations on packed data

Microarchitecture for implementing an instruction to clear the tags of a stack reference register file

Processor with instructions that operate on different data types stored in the same single logical register file

System for controlling arbitration using the memory request signal types generated by the plurality of datapaths

System with plurality of datapaths having dual-ported local memory architecture for converting prefetched variable length data to fixed length decoded data

Method and apparatus for performing multiply-add operations on packed data

Methods and apparatuses to clear state for operation of a stack

System for controlling arbitration using the memory request signal types generated by the plurality of datapaths having dual-ported local memory architecture for simultaneous data transmission

Emptying packed data state during execution of packed data instructions

Computer implemented method for providing a two dimensional rotation of packed data

Processor for performing multiply-add operations on packed data

PELEG ALEXANDER

Processor for performing multiply-add operations on packed data

Method and apparatus for performing multiply-add operations on packed data

Processor for performing multiply-add operations on packed data

PELEG ALEXANDER D

Processor for performing multiply-add operations on packed data

Processor for performing multiply-add operations on packed data

Method for performing complex fast fourier transforms (FFT's)