Inventor

RAJWADE SHANTANU R

US28 patents

⚠️ This page may combine multiple inventors who share the name “RAJWADE SHANTANU R”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

RAJWADE SHANTANU R

INTEL CORP

Method and apparatus for protecting lower page data during programming in NAND flash

Method and apparatus for dynamically determining start program voltages for a memory device

Method and apparatus for reducing data program completion overhead in NAND flash

Segmented erase in memory

Performing read operations on a memory device

Boosted bitlines for storage cell programmed state verification in a memory array

Method and apparatus for improving sequential reading in NAND flash

SSD having a parallelized, multi-level program voltage verification

Using variable voltages to discharge electrons from a memory array during verify recovery operations

Method and apparatus for improving write uniformity in a memory device

Cache processes with adaptive dynamic start voltage calculation for memory devices

Ramping inhibit voltage during memory programming

Ramping inhibit voltage during memory programming

Method and apparatus for dynamically determining start program voltages for a memory device

Predictive count fail byte (CFBYTE) for non-volatile memory

MICRON TECHNOLOGY INC

Apparatuses and methods for concurrently accessing multiple memory planes of a memory during a memory access operation

Apparatuses and methods for concurrently accessing multiple memory planes of a memory during a memory access operation

Apparatuses and methods for concurrently accessing multiple memory planes of a memory during a memory access operation

Buffer operations in memory

Apparatuses and methods for concurrently accessing multiple memory planes of a memory during a memory access operation

Buffer operations in memory

Intel NDTM US LLC

Efficient bitline stabilization for program inhibit in NAND arrays

Dynamic detection and dynamic adjustment of sub-threshold swing in a memory cell sensing circuit

Program verify process having placement aware pre-program verify (PPV) bucket size modulation

Skip program verify for dynamic start voltage sampling

Memory cell sensing circuit with adjusted bias from pre-boost operation

RAJWADE SHANTANU R

Ramping inhibit voltage during memory programming

SK HYNIX NAND PRODUCT SOLUTIONS CORP

Solid state drive (SSD) with in-flight erasure iteration suspension