Inventor

GUTTAG KARL M

US136 patents

⚠️ This page may combine multiple inventors who share the name “GUTTAG KARL M”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

GUTTAG KARL M

TEXAS INSTRUMENTS INC

Data processing system with register store/load utilizing data packing/unpacking

Long instruction word controlling plural independent processor operations

Three input arithmetic logic unit with shifter and/or mask generator

Apparatus and system for sum of plural absolute differences

Arithmetic logic unit with conditional register source selection

Base address generation in a multi-processing system having plural memories with a unified address space corresponding to each processor

Reconfigurable SIMD/MIMD processor using switch matrix to allow access to a parameter memory by any of the plurality of processors

Address generator with controllable modulo power of two addressing capability

Three input arithmetic logic unit forming mixed arithmetic and boolean combinations

Multiple operations employing divided arithmetic logic unit and multiple flags register

Three input arithmetic logic unit with mask generator

Reconfigurable multi-processor operating in SIMD mode with one processor fetching instructions for use by remaining processors

Multi-processor with crossbar link of processors and memories and method of operation

Multi-processor having control over synchronization of processors in mind mode and method of operation

Dual mode SIMD/MIMD processor providing reuse of MIMD instruction memories as data memories when operating in SIMD mode

Multi-processor reconfigurable in single instruction multiple data (SIMD) and multiple instruction multiple data (MIMD) modes and method of operation

Random/serial access mode selection circuit for a video memory system

Data processing device formed on a single semiconductor substrate having secure memory

Data processing apparatus with indirect register file access

Three input arithmetic logic unit with shifter

Arithmetic logic unit having plural independent sections and register storing resultant indicator bit from every section

Plural memory access address generation employing guide table entries forming linked list

System including a data processor, a synchronous dram, a peripheral device, and a system clock

Video display system using memory with parallel and serial access employing serial shift registers selected by column address

Graphics data processing apparatus having image operations with transparent color having a selectable number of bits

Control of data access to memory for improved video system

Data processor having capability to perform both floating point operations and memory access in response to a single instruction

Video display system using memory with parallel and serial access employing serial shift registers selected by column address

Video display system using memory with parallel and serial access employing selectable cascaded serial shift registers

Security bit for designating the security status of information stored in a nonvolatile memory

Long instruction word controlling plural independent processor operations

Data processor with flexible multiply unit

Instruction having bit field designating status bits protected from modification corresponding to arithmetic logic unit result

Three input arithmetic logic unit with barrel rotator

Long instruction word controlling plural independent processor operations

Method, apparatus and system forming the sum of data in plural equal sections of a single data word

Three input arithmetic logic unit capable of performing all possible three operand boolean operations with shifter and/or mask generator

Three input arithmetic logic unit with barrel rotator and mask generator

Memory configuration cache with multilevel hierarchy least recently used cache entry replacement

Long instruction word controlling plural independent processor operations

Hardware branching employing loop control registers loaded according to status of sections of an arithmetic logic unit divided into a plurality of sections

Three input arithmetic logic unit with shifting means at one input forming a sum/difference of two inputs logically anded with a third input logically ored with the sum/difference logically anded with an inverse of the third input

Memory store from a selected one of a register pair conditional upon the state of a selected status bit

Three input arithmetic logic unit with controllable shifter and mask generator

Three input arithmetic logic unit with mask generator

Random access memory arranged for operating synchronously with a microprocessor and a system including a data processor, a synchronous DRAM, a peripheral device, and a system clock

Transfer processor with transparency

Architecture of transfer processor

(unassigned)

Long instruction word controlling plural independent processor operations

SYNDIANT INC

Recursive feedback control of light modulating elements