Inventor
VILLARRUBIA PAUL GERARD
US15 patents
Patents
15 patentsUS6996512B2Feb 7, 2006
Practical methodology for early buffer and wire resource allocation
IBM60 citations96
US6080201AJun 27, 2000
Integrated placement and synthesis for timing closure of microprocessors
IBM74 citations94
US5838582ANov 17, 1998
Method and system for performing parasitic capacitance estimations on interconnect data within an integrated circuit
IBM31 citations92
US6360350B1Mar 19, 2002
Method and system for performing circuit analysis on an integrated-circuit design having design data available in different forms
IBM39 citations91
US6230302B1May 8, 2001
Method and system for performing timing analysis on an integrated circuit design
IBM20 citations91
US6086238AJul 11, 2000
Method and system for shape processing within an integrated circuit layout for parasitic capacitance estimation
IBM27 citations91
US6510540B1Jan 21, 2003
Windowing mechanism for reducing pessimism in cross-talk analysis of digital chips
IBM29 citations90
US6286007B1Sep 4, 2001
Method and system for efficiently storing and viewing data in a database
IBM33 citations90
US7047163B1May 16, 2006
Method and apparatus for applying fine-grained transforms during placement synthesis interaction
IBM25 citations89
US5831870ANov 3, 1998
Method and system for characterizing interconnect data within an integrated circuit for facilitating parasitic capacitance estimation
IBM46 citations89
US7073144B2Jul 4, 2006
Stability metrics for placement to quantify the stability of placement algorithms
IBM14 citations84
US7296252B2Nov 13, 2007
Clustering techniques for faster and better placement of VLSI circuits
IBM17 citations81
US7020861B2Mar 28, 2006
Latch placement technique for reduced clock signal skew
IBM16 citations81
US7464356B2Dec 9, 2008
Method and apparatus for diffusion based cell placement migration
IBM7 citations74
US5966522AOct 12, 1999
Multi-phase clock distribution method and system for complex integrated-circuit devices
IBM4 citations59