Inventor

BYBELL ANTHONY J

US36 patents

⚠️ This page may combine multiple inventors who share the name “BYBELL ANTHONY J”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

BYBELL ANTHONY J

IBM

System and method for supporting access to multiple I/O hub nodes in a host bridge

Managing translations across multiple contexts using a TLB with entries directed to multiple privilege levels and to multiple types of address spaces

Managing translation of a same address across multiple contexts using a same entry in a translation lookaside buffer

Selectable address translation mechanisms

Managing translations across multiple contexts using a TLB with entries directed to multiple privilege levels and to multiple types of address spaces

Systems, methods and computer products for compression of hierarchical identifiers

Hybrid address translation

Identification and consolidation of page table entries

Method and system for broadcasting data to multiple tap controllers

Hardware-based pre-page walk virtual address transformation independent of page size utilizing bit shifting based on page size

Hardware-based pre-page walk virtual address transformation where the virtual address is shifted by current page size and a minimum page size

Radix table translation of memory

Page table entry consolidation

Separate memory address translations for instruction fetches and data accesses

Separate memory address translations for instruction fetches and data accesses

Managing translation of a same address across multiple contexts using a same entry in a translation lookaside buffer

Asymmetric co-existent address translation structure formats

Asymmetric co-existent address translation structure formats

Method for providing zero overhead looping using carry chain masking

BYBELL ANTHONY J

System and apparatus for error-correcting register files

Radix table translation of memory

Utilizing error correcting code data associated with a region of memory

Hybrid address translation

Multi-threaded processing

Cache function overloading

Fine-grained privilege escalation

Page table entry consolidation

Identification and consolidation of page table entries

Structure for cache function overloading

Structure for multi-threaded processing

Routing instructions in a processor

ADVANCED MICRO DEVICES INC

Processor with multiple fetch and decode pipelines

Processor with multiple op cache pipelines

Method and apparatus for power reduction in a multi-threaded mode

Method and apparatus for power reduction in a multi-threaded mode

Updating least-recently-used data for greater persistence of higher generality cache entries