Inventor

GROT BORIS

CH7 patents

⚠️ This page may combine multiple inventors who share the name “GROT BORIS”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

GRATZ PAUL

2 patents

US8285900B2Oct 9, 2012

Method and apparatus for congestion-aware routing in a computer interconnection network

GRATZ PAUL15 citations88

US8694704B2Apr 8, 2014

Method and apparatus for congestion-aware routing in a computer interconnection network

GRATZ PAUL6 citations75

UNIV COURT UNIV OF EDINBURGH

2 patents

US11269641B2Mar 8, 2022

Branch target buffer for a data processing apparatus

UNIV COURT UNIV OF EDINBURGH3 citations68

US11544066B2Jan 3, 2023

Branch target buffer arrangement with preferential storage for unconditional branch instructions

UNIV COURT UNIV OF EDINBURGH1 citations62

KECKLER STEPHEN W

1 patent

US8307116B2Nov 6, 2012

Scalable bus-based on-chip interconnection networks

KECKLER STEPHEN W9 citations78

ECOLE POLYTECHNIQUE FED DE LAUSANNE (EPFL)

1 patent

US9703707B2Jul 11, 2017

Network-on-chip using request and reply trees for low-latency processor-memory communication

ECOLE POLYTECHNIQUE FED DE LAUSANNE (EPFL)10 citations77

UNIV TEXAS

1 patent

US9571399B2Feb 14, 2017

Method and apparatus for congestion-aware routing in a computer interconnection network

UNIV TEXAS0 citations50