Inventor
IYENGAR SUNDARAVARATHAN R
US11 patents
⚠️ This page may combine multiple inventors who share the name “IYENGAR SUNDARAVARATHAN R”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
9 patentsUS5210845AMay 11, 1993
Controller for two-way set associative cache
INTEL CORP75 citations95
US5699548ADec 16, 1997
Method and apparatus for selecting a mode for updating external memory
INTEL CORP67 citations91
US5530833AJun 25, 1996
Apparatus and method for updating LRU pointer in a controller for two-way set associative cache
INTEL CORP18 citations81
US5392417AFeb 21, 1995
Processor cycle tracking in a controller for two-way set associative cache
INTEL CORP7 citations73
US5367659ANov 22, 1994
Tag initialization in a controller for two-way set associative cache
INTEL CORP18 citations73
US5669014ASep 16, 1997
System and method having processor with selectable burst or no-burst write back mode depending upon signal indicating the system is configured to accept bit width larger than the bus width
INTEL CORP11 citations72
US8904205B2Dec 2, 2014
Increasing power efficiency of turbo mode operation in a processor
INTEL CORP4 citations71
US8683240B2Mar 25, 2014
Increasing power efficiency of turbo mode operation in a processor
INTEL CORP4 citations71
US5768558AJun 16, 1998
Identification of the distinction between the beginning of a new write back cycle and an ongoing write cycle
INTEL CORP6 citations61