Inventor

KALB JR JEFFREY C

US13 patents

⚠️ This page may combine multiple inventors who share the name “KALB JR JEFFREY C”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

INTEL CORP

10 patents

US5742177AApr 21, 1998

Method for testing a semiconductor device by measuring quiescent currents (IDDQ) at two different temperatures

INTEL CORP55 citations95

US5889409AMar 30, 1999

Leakage tracking device sample for IDDQ measurement and defect resolution

INTEL CORP22 citations92

US5627789AMay 6, 1997

Sense amplifier circuitry for differential semiconductor memories

INTEL CORP51 citations92

US5801533ASep 1, 1998

Method and apparatus with cascode biasing magneto field effect transistors for improved sensitivity and amplification

INTEL CORP18 citations83

US5986461ANov 16, 1999

UV methods for screening open circuit defects in CMOS integrated circuits

INTEL CORP16 citations81

US6242934B1Jun 5, 2001

Background leakage zeroing by temperature and voltage dependence for IDDQ measurement and defect resolution

INTEL CORP9 citations73

US5760581AJun 2, 1998

Method and apparatus coupling together magneto field effect transistors in series to accumulate the effects of magnetic field for improved sensitivity and linearity

INTEL CORP7 citations73

US5757055AMay 26, 1998

Triple drain magneto field effect transistor with high conductivity central drain

INTEL CORP10 citations73

US5869977AFeb 9, 1999

Defect insertion testability mode for IDDQ testing methods

INTEL CORP13 citations66

US6107817AAug 22, 2000

UV methods for screening open circuit defects in CMOS integrated circuits

INTEL CORP1 citations51

MICRO DEVICES CORP CALIFORNIA

3 patents

US6100713AAug 8, 2000

KALB JR JEFFREY C

INTEL CORP

Method for testing a semiconductor device by measuring quiescent currents (IDDQ) at two different temperatures

Leakage tracking device sample for IDDQ measurement and defect resolution

Sense amplifier circuitry for differential semiconductor memories

Method and apparatus with cascode biasing magneto field effect transistors for improved sensitivity and amplification

UV methods for screening open circuit defects in CMOS integrated circuits

Background leakage zeroing by temperature and voltage dependence for IDDQ measurement and defect resolution

Method and apparatus coupling together magneto field effect transistors in series to accumulate the effects of magnetic field for improved sensitivity and linearity

Triple drain magneto field effect transistor with high conductivity central drain

Defect insertion testability mode for IDDQ testing methods

UV methods for screening open circuit defects in CMOS integrated circuits

MICRO DEVICES CORP CALIFORNIA

Termination circuits and methods for memory buses and devices

Termination circuits and methods therefor

Termination circuits and methods for bused and networked devices