Inventor

YOO JEI-HWAN

KR36 patents

Patents

36 patents

US5761146AJun 2, 1998

Data in/out channel control circuit of semiconductor memory device having multi-bank structure

SAMSUNG ELECTRONICS CO LTD145 citations98

US6560158B2May 6, 2003

Power down voltage control method and apparatus

SAMSUNG ELECTRONICS CO LTD101 citations97

US6937087B2Aug 30, 2005

Temperature sensor and method for detecting trip temperature of a temperature sensor

SAMSUNG ELECTRONICS CO LTD55 citations96

US6545923B2Apr 8, 2003

Negatively biased word line scheme for a semiconductor memory device

SAMSUNG ELECTRONICS CO LTD64 citations96

US5617366AApr 1, 1997

Method and apparatus for a test control circuit of a semiconductor memory device

SAMSUNG ELECTRONICS CO LTD69 citations96

US7106127B2Sep 12, 2006

Temperature sensor and method for detecting trip temperature of a temperature sensor

SAMSUNG ELECTRONICS CO LTD30 citations93

US6456555B2Sep 24, 2002

Circuit and method for controlling a redundant memory cell in an integrated memory circuit

SAMSUNG ELECTRONICS CO LTD31 citations92

US5856952AJan 5, 1999

Integrated circuit memory devices including a plurality of row latch circuits and related methods

SAMSUNG ELECTRONICS CO LTD20 citations92

US5798978AAug 25, 1998

Semiconductor memory device with multibank structure

SAMSUNG ELECTRONICS CO LTD17 citations92

US5751642AMay 12, 1998

Voltage control circuit for input and output lines of semiconductor memory device

SAMSUNG ELECTRONICS CO LTD26 citations92

US5638331AJun 10, 1997

Burn-in test circuit and method in semiconductor memory device

SAMSUNG ELECTRONICS CO LTD44 citations87

US7023262B2Apr 4, 2006

Negative voltage generator for a semiconductor memory device

SAMSUNG ELECTRONICS CO LTD17 citations84

US6490222B2Dec 3, 2002

Decoding circuit for controlling activation of wordlines in a semiconductor memory device

SAMSUNG ELECTRONICS CO LTD15 citations84

US6424578B2Jul 23, 2002

Voltage detecting circuit for semiconductor memory device

SAMSUNG ELECTRONICS CO LTD15 citations84

US5715209AFeb 3, 1998

Integrated circuit memory devices including a dual transistor column selection switch and related methods

SAMSUNG ELECTRONICS CO LTD17 citations84

US6335897B1Jan 1, 2002

Semiconductor memory device including redundancy circuit adopting latch cell

SAMSUNG ELECTRONICS CO LTD11 citations74

US6151264ANov 21, 2000

Integrated circuit memory devices including a single data shift block between first and second memory banks

SAMSUNG ELECTRONICS CO LTD8 citations74

US6064601AMay 16, 2000

Integrated circuit memory devices and controlling methods that simultaneously activate multiple column select lines during a write cycle of a parallel bit test mode

SAMSUNG ELECTRONICS CO LTD13 citations74

US5657265AAug 12, 1997

Semiconductor memory device having circuit array structure for fast operation

SAMSUNG ELECTRONICS CO LTD8 citations74

US5650977AJul 22, 1997

Integrated circuit memory device including banks of memory cells and related methods

SAMSUNG ELECTRONICS CO LTD14 citations74

US6829189B2Dec 7, 2004

Semiconductor memory device and bit line sensing method thereof

SAMSUNG ELECTRONICS CO LTD9 citations73

US5715210AFeb 3, 1998

Low power semiconductor memory device

SAMSUNG ELECTRONICS CO LTD10 citations73

US7336121B2Feb 26, 2008

Negative voltage generator for a semiconductor memory device

SAMSUNG ELECTRONICS CO LTD5 citations63

US6590237B2Jul 8, 2003

Layout structure for dynamic random access memory

SAMSUNG ELECTRONICS CO LTD3 citations63

US6400620B1Jun 4, 2002

Semiconductor memory device with burn-in test function

SAMSUNG ELECTRONICS CO LTD6 citations63

US6252808B1Jun 26, 2001

Semiconductor memory device having improved row redundancy scheme and method for curing defective cell

SAMSUNG ELECTRONICS CO LTD4 citations63

US6927488B2Aug 9, 2005

Semiconductor memory device

SAMSUNG ELECTRONICS CO LTD2 citations62

US6845049B2Jan 18, 2005

Semiconductor memory device including a delaying circuit capable of generating a delayed signal with a substantially constant delay time

SAMSUNG ELECTRONICS CO LTD6 citations62

US6178109B1Jan 23, 2001

Integrated circuit memory devices having reduced susceptibility to reference voltage signal noise

SAMSUNG ELECTRONICS CO LTD4 citations62

US6252263B1Jun 26, 2001

Layout structure for dynamic random access memory

SAMSUNG ELECTRONICS CO LTD1 citations52

US5784322AJul 21, 1998

Standby current detecting circuit for use in a semiconductor memory device and method thereof

SAMSUNG ELECTRONICS CO LTD1 citations52

YOO JEI-HWAN

Patents

Data in/out channel control circuit of semiconductor memory device having multi-bank structure

Power down voltage control method and apparatus

Temperature sensor and method for detecting trip temperature of a temperature sensor

Negatively biased word line scheme for a semiconductor memory device

Method and apparatus for a test control circuit of a semiconductor memory device

Temperature sensor and method for detecting trip temperature of a temperature sensor

Voltage detecting circuit for semiconductor memory device

Power down voltage control method and apparatus

Semiconductor memory device having redundancy function

Memory sub-word line driver operated by unboosted voltage

High speed test circuit for a semiconductor memory device

Circuit and method for controlling a redundant memory cell in an integrated memory circuit

Integrated circuit memory devices including a plurality of row latch circuits and related methods

Semiconductor memory device with multibank structure

Voltage control circuit for input and output lines of semiconductor memory device

Burn-in test circuit and method in semiconductor memory device

Negative voltage generator for a semiconductor memory device

Decoding circuit for controlling activation of wordlines in a semiconductor memory device

Voltage detecting circuit for semiconductor memory device

Integrated circuit memory devices including a dual transistor column selection switch and related methods

Semiconductor memory device including redundancy circuit adopting latch cell

Integrated circuit memory devices including a single data shift block between first and second memory banks

Integrated circuit memory devices and controlling methods that simultaneously activate multiple column select lines during a write cycle of a parallel bit test mode

Semiconductor memory device having circuit array structure for fast operation

Integrated circuit memory device including banks of memory cells and related methods

Semiconductor memory device and bit line sensing method thereof

Low power semiconductor memory device

Negative voltage generator for a semiconductor memory device

Layout structure for dynamic random access memory

Semiconductor memory device with burn-in test function

Semiconductor memory device having improved row redundancy scheme and method for curing defective cell

Semiconductor memory device

Semiconductor memory device including a delaying circuit capable of generating a delayed signal with a substantially constant delay time

Integrated circuit memory devices having reduced susceptibility to reference voltage signal noise

Layout structure for dynamic random access memory

Standby current detecting circuit for use in a semiconductor memory device and method thereof