Inventor

WASSICK THOMAS A

US43 patents

⚠️ This page may combine multiple inventors who share the name “WASSICK THOMAS A”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

WASSICK THOMAS A

IBM

Selective metal etching in metal/polymer structures

UV-curable compositions and method of use thereof in microelectronics

Inherently robust repair process for thin film circuitry using UV laser

Structure for repairing electrical lines

Method and structure for repairing electrical lines

Laser-induced chemical vapor deposition of thin-film conductors

Under ball metallurgy (UBM) for improved electromigration

Sensor, method, and design structure for a low-k delamination sensor

Inherently robust repair process for thin film circuitry using uv laser

Seed metal delete process for thin film repair solutions using direct UV laser

Determining crackstop strength of integrated circuit assembly at the wafer level

Lead-free solder joining of electronic structures

All intermetallic compound with stand off feature and method to make

Top-surface-metallurgy plate-up bonding and rewiring for multilayer devices

In-line voltage plane tests for multi-chip modules

Method and structure for top-to-bottom I/O nets repair in a thin film transfer and join process

Organic coating to inhibit solder wetting on pillar sidewalls

Elastic modulus mapping of an integrated circuit chip in a chip/device package

Lead-free solder joining of electronic structures

Electronic package repair process

Method of selective plating on a substrate

Process of top-surface-metallurgy plate-up bonding and rewiring for multilayer devices

Top-surface-metallurgy plate-up bonding and rewiring for multilayer devices

Thin film device repaired using enhanced repair process

Enhanced thin film wiring net repair process

Graphics assisted manufacturing process for thin-film devices

Three-dimensional integrated circuit integration

Three-dimensional integrated circuit integration

Mitigating cracking within integrated circuit (IC) device carrier

Structures and methods to reduce maximum current density in a solder ball

Test cell for laminate and method

Test cell for laminate and method

Under ball metallurgy (UBM) for improved electromigration

Compressive zone to reduce dicing defects

Electronic package repair process

Managing interconnect electromigration effects

Step pyramid shaped structure to reduce dicing defects

GLOBALFOUNDRIES INC

Semiconductor device contact structure having stacked nickel, copper, and tin layers

Multilayered contact structure having nickel, copper, and nickel-iron layers

Electromigration-resistant lead-free solder interconnect structures

DAUBENSPECK TIMOTHY H

Offset solder vias, methods of manufacturing and design structures

BEZAMA RASCHID J

Structures and methods to reduce maximum current density in a solder ball

INTERRANTE MARIO J

Semiconductor structure having offset passivation to reduce electromigration