Inventor

IWAHASHI HIROSHI

JP125 patents

⚠️ This page may combine multiple inventors who share the name “IWAHASHI HIROSHI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

IWAHASHI HIROSHI

TOSHIBA KK

Non-volatile semiconductor memory device and data programming method

Non-volatile semiconductor memory device with programming voltage generating system and data programming method

Semiconductor memory device

Semiconductor memory device

Electrically programmable nonvolatile semiconductor memory device with NAND cell structure

Nonvolatile semiconductor memory device

Semiconductor memory device capable of storing plural-bit data in a single memory cell

Nonvolatile semiconductor memory device

Electrically programmable nonvolatile semiconductor memory device with nand cell structure

Semiconductor memory device with a sense amplifier

Electrically-erasable/programmable nonvolatile semiconductor memory device

High voltage booster circuit for use in EEPROMs

Nonvolatile semiconductor memory device with readout test circuitry

Non-volatile semiconductor memory device and data programming method

Nonvolatile semiconductor memory device

Non-volatile semiconductor memory device with a plurality of programming voltage levels

Non-volatile semiconductor memory device and method of manufacturing the same

Semiconductor memory device having a data detection circuit with two reference potentials

Electrically programmable nonvolatile semiconductor memory device with nand cell structure

Input circuit of semiconductor integrated circuit and semiconductor integrated circuit having input circuit

Electrically programmable nonvolatile semiconductor memory device with NAND cell structure

Semiconductor memory having a stabalized reference potential for use in detecting a data read out from a memory cell

Semiconductor integrated circuit with a circuit limiting an input voltage to a predetermined voltage

Voltage detecting circuit

Semiconductor memory device with plural latches for read out

Non-volatile semiconductor memory and method of manufacturing the same

Non-volatile semiconductor memory with NAND cell structure and switching transistors with different channel lengths to reduce punch-through

Semiconductor memory device having redundant memory cells

Non-volatile semiconductor memory and method of manufacturing the same

Semiconductor integrated circuit

Semiconductor memory device with address transition actuated dummy cell

Semiconductor memory device having transfer gates which prevent high voltages from being applied to memory and dummy cells in the reading operation

Semiconductor memory device having a majority logic for determining data to be read out

Delay circuit that resets after pulse-like noise

Electrically erasable non-volatile semiconductor device

Output circuit of semiconductor integrated circuit device

TOKYO SHIBAURA ELECTRIC CO

Non-volatile semiconductor memory system

Semiconductor memory with delay means to reduce peak currents

Semiconductor device

Semiconductor memory device

Semiconductor IC memory

Semiconductor integrated circuit with a response time compensated with respect to temperature

Semiconductor memory device

Logic circuit having voltage booster

Semiconductor memory with selectively enabled precharge and sense amplifier circuits

Non-volatile semiconductor memory system

Nonvolatile semiconductor memory device

Multifunction terminal circuit

Semiconductor memory with pulse controlled column load circuit

(unassigned)

Non-volatile semiconductor memory device and data programming method