Inventor

SESHAN KRISHNA

US56 patents

⚠️ This page may combine multiple inventors who share the name “SESHAN KRISHNA”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SESHAN KRISHNA

INTEL CORP

Device with segmented ball limiting metallurgy

Ball limiting metallurgy for input/outputs and methods of fabrication

Process for sort testing C4 bumped wafers

Mobile computer having a housing with openings for cooling

Energy-absorbing stable guard ring

Planar guard ring

Isolation structure configurations for modifying stresses in semiconductor devices

Method of forming segmented ball limiting metallurgy

Selectable decoupling capacitors for integrated circuit and methods of use

Ball limiting metallurgy for input/outputs and methods of fabrication

Mobile computer having a housing with openings for cooling

Electronic assembly and cooling thereof

Electronic assembly and cooling thereof

Semiconductor passivation deposition process for interfacial adhesion

Method to reduce timing skews in I/O circuits and clock drivers caused by fabrication process tolerances

Ball-limiting metallurgies, solder bump compositions used therewith, packages assembled thereby, and methods of assembling same

Planar guard ring

Passivation technology combining improved adhesion in passivation and a scribe street without passivation

Integrated passivation process, probe geometry and probing process

KLXX technology with integrated passivation process, probe geometry and probing process

Integrated circuit package

Method and apparatus for cutting a wafer

Selectable decoupling capacitors for integrated circuits and associated methods

Diode and transistor design for high speed I/O

Metal locking structures to prevent a passivation layer from delaminating

Ball-limiting metallurgies, solder bump compositions used therewith, packages assembled thereby, and methods of assembling same

Integrated circuit package

Power gridding scheme

Selectable decoupling capacitors for integrated circuit and methods of use

Method and apparatus for a linearized output driver and terminator

Diode and transistor design for high speed I/O

Metal staples to prevent interlayer delamination

Wire-bond process flow for copper metal-six, structures achieved thereby, and testing method

Isolation structure configurations for modifying stresses in semiconductor devices

Isolation structure configurations for modifying stresses in semiconductor devices

Silicon wafer testing rig and a method for testing a silicon wafer wherein the silicon wafer is bent into a dome shape

Method for fabricating a moat around an active pixel area of a microelectronic image projection device

Energy absorbing structures to prevent damage to an integrated circuit

Method of fabricating a linearized output driver and terminator

Power gridding scheme

IBM

Electrically programmable antifuse using metal penetration of a junction

Method of making a self cooling electrically programmable fuse

Method of forming a thermally activated noise immune fuse

Self cooling electrically programmable fuse

Thermally activated noise immune fuse

Ultrasonic adhesion/dehesion monitoring apparatus with power feedback measuring means

Ultrasonic adhesion/dehesion monitoring apparatus with acoustic transducer means

On-chip temperature sensor utilizing a Schottky barrier diode structure

Instrument for the measurement of electrical characteristics during manufacturing processes

Method and apparatus for causing an open circuit in a conductive line