Inventor
WAJDA CORY
US28 patents
⚠️ This page may combine multiple inventors who share the name “WAJDA CORY”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
TOKYO ELECTRON LTD
23 patentsUS6500761B1Dec 31, 2002
Method for improving the adhesion and durability of CVD tantalum and tantalum nitride modulated films by plasma treatment
TOKYO ELECTRON LTD21 citations92
US10068764B2Sep 4, 2018
Selective metal oxide deposition using a self-assembled monolayer surface pretreatment
TOKYO ELECTRON LTD7 citations84
US7393761B2Jul 1, 2008
Method for fabricating a semiconductor device
TOKYO ELECTRON LTD7 citations73
US11024535B2Jun 1, 2021
Method for filling recessed features in semiconductor devices with a low-resistivity metal
TOKYO ELECTRON LTD4 citations71
US10991881B2Apr 27, 2021
Method for controlling the forming voltage in resistive random access memory devices
TOKYO ELECTRON LTD2 citations71
US10157784B2Dec 18, 2018
Integration of a self-forming barrier layer and a ruthenium metal liner in copper metallization
TOKYO ELECTRON LTD4 citations71
US9607888B2Mar 28, 2017
Integration of ALD barrier layer and CVD Ru liner for void-free Cu filling
TOKYO ELECTRON LTD2 citations71
US7300891B2Nov 27, 2007
Method and system for increasing tensile stress in a thin film using multi-frequency electromagnetic radiation
TOKYO ELECTRON LTD7 citations70
US7964515B2Jun 21, 2011
Method of forming high-dielectric constant films for semiconductor devices
TOKYO ELECTRON LTD5 citations63
US11700778B2Jul 11, 2023
Method for controlling the forming voltage in resistive random access memory devices
TOKYO ELECTRON LTD0 citations61
US11621190B2Apr 4, 2023
Method for filling recessed features in semiconductor devices with a low-resistivity metal
TOKYO ELECTRON LTD0 citations61
US7470591B2Dec 30, 2008
Method of forming a gate stack containing a gate dielectric layer having reduced metal content
TOKYO ELECTRON LTD4 citations60
US7501352B2Mar 10, 2009
Method and system for forming an oxynitride layer
TOKYO ELECTRON LTD3 citations58
US7479454B2Jan 20, 2009
Method and processing system for monitoring status of system components
TOKYO ELECTRON LTD3 citations57
US10700009B2Jun 30, 2020
Ruthenium metal feature fill for interconnects
TOKYO ELECTRON LTD0 citations51
US10056328B2Aug 21, 2018
Ruthenium metal feature fill for interconnects
TOKYO ELECTRON LTD1 citations51
US9711449B2Jul 18, 2017
Ruthenium metal feature fill for interconnects
TOKYO ELECTRON LTD1 citations51
US12588435B2Mar 24, 2026
Selective inhibition for selective metal deposition
TOKYO ELECTRON LTD0 citations50
US12482667B2Nov 25, 2025
Thermal etching of ruthenium
TOKYO ELECTRON LTD0 citations50
US12237216B2Feb 25, 2025
Method for filling recessed features in semiconductor devices with a low-resistivity metal
TOKYO ELECTRON LTD0 citations50
US10950460B2Mar 16, 2021
Method utilizing using post etch pattern encapsulation
TOKYO ELECTRON LTD0 citations50
US10008564B2Jun 26, 2018
Method of corner rounding and trimming of nanowires by microwave plasma
TOKYO ELECTRON LTD0 citations50
US7419702B2Sep 2, 2008
Method for processing a substrate
TOKYO ELECTRON LTD1 citations49
IBM
3 patentsUS6974779B2Dec 13, 2005
Interfacial oxidation process for high-k gate dielectric process integration
IBM20 citations91
US7235440B2Jun 26, 2007
Formation of ultra-thin oxide layers by self-limiting interfacial oxidation
IBM5 citations59
US7202186B2Apr 10, 2007
Method of forming uniform ultra-thin oxynitride layers
IBM1 citations49