Inventor

CHAUVEL GERARD

FR117 patents

⚠️ This page may combine multiple inventors who share the name “CHAUVEL GERARD”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CHAUVEL GERARD

TEXAS INSTRUMENTS INC

Video display control system having improved storage of alphanumeric and graphic display data

Temperature field controlled scheduling for processing systems

JAVA DSP acceleration by byte-code optimization

Task based adaptative profiling and debugging

Dynamic hardware control for energy management systems using task attributes

Dynamic hardware configuration for energy management systems using task attributes

TLB operation based on task-ID

Audio and video decoder circuit and system

Method and system for processing a “WIDE” opcode when it is not used as a prefix for an immediately following opcode

System and method for executing tasks according to a selected scenario in response to probabilistic power consumption information of each scenario

TLB operations based on shared bit

Multiple microprocessors with a shared cache

Software controlled cache configuration based on average miss rate

Video image processing system

Video display system

Unified memory management system for multi processor heterogeneous architecture

Traffic controller using priority and burst control for reducing access latency

Memory control using memory state information for reducing access latency

Real time window address calculation for on-screen display

Transport stream packet parser system

Using IMPDEP2 for system commands related to Java accelerator hardware

Priority arbitration based on current task and MMU

TLB lock and unlock operation

Fault management and recovery based on task-ID

Cache and DMA with a global valid bit

Interruptible and re-entrant cache clean range instruction

MMU descriptor having big/little endian bit to control the transfer data between devices

Cache with DMA and dirty bits

Level 2 smartcache architecture supporting simultaneous multiprocessor accesses

Master/slave processing system with shared translation lookaside buffer

Level 2 cache architecture for multiprocessor with task—ID and resource—ID

TLB with resource ID field

Cache with block prefetch and DMA

Task based priority arbitration

Cache/smartcache with interruptible block prefetch

Video system with combined text and graphics frame memory

System for displaying graphic information on video screen employing video display processor

Memory access controller having cycle number register for storing the number of column address cycles in a multiple column address/single row address memory access cycle

Method and system for accessing indirect memories

System and method to automatically stack and unstack Java local variables

Smart cache

Digital filtering with single-instruction, multiple-data processor

Method and apparatus for providing and on-screen display with variable resolution capability

Cache optimization for programming loops

Tasks distribution in a multi-processor including a translation lookaside buffer shared between processors

Inter-processor control

Conditional garbage based on monitoring to improve real time performance

CHAUVEL GERARD

Compare instruction

Dirty cache line write back policy based on stack size trend information

Performing java interrupt with two program counters