Inventor

AVANZINO STEVEN C

US84 patents

⚠️ This page may combine multiple inventors who share the name “AVANZINO STEVEN C”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

AVANZINO STEVEN C

ADVANCED MICRO DEVICES INC

Optimized trench/via profile for damascene filling

Optimized trench/via profile for damascene processing

Chemical solutions for removing metal-compound contaminants from wafers after CMP and the method of wafer cleaning

Interconnect structure formed in porous dielectric material with minimized degradation and electromigration

Protection low-k ILD during damascene processing with thin liner

Conformal barrier liner in an integrated circuit interconnect

Method of fabricating improved copper metallization including forming and removing passivation layer before forming capping film

Low-k photoresist removal process

Copper dendrite prevention by chemical removal of dielectric

Optimized trench/via profile for damascene filling

Method for multiple phase polishing of a conductive layer in a semidonductor wafer

Method of preventing copper dendrite formation and growth

Methodology for developing product-specific interlayer dielectric polish processes

Method of planarization of topologies in integrated circuit structures

Chemical-mechanical polishing slurry formulation and method for tungsten and titanium thin films

Solutions for controlled, selective etching of copper

Conformal barrier liner in an integrated circuit interconnect

Protection of low-k ILD during damascene processing with thin liner

Scatterometry of grating structures to monitor wafer stress

Sensor to predict void free films using various grating structures and characterize fill performance

Metal bridging monitor for etch and CMP endpoint detection

Methods of forming capped copper interconnects with improved electromigration resistance

Interconnect methodology employing a low dielectric constant etch stop layer

Wafer based temperature sensors for characterizing chemical mechanical polishing processes

Method of forming capped copper interconnects with reduced hillock formation and improved electromigration resistance

Method of copper-polysilicon T-gate formation

Integrated circuit with dielectric diffusion barrier layer formed between interconnects and interlayer dielectric layers

Tantalum anodization for in-laid copper metallization capacitor

Method of improving electromigration resistance of capped Cu

Method and apparatus for improved planarity metallization by electroplating and CMP

Bilayer interlayer dielectric having a substantially uniform composite interlayer dielectric constant over pattern features of varying density and method of making the same

Optimized trench/via profile for damascene filling

Sputter-resistant hardmask for damascene trench/via formation

Memory cell and method of making the memory cell

Chemically preventing Cu dendrite formation and growth by immersion

Ta barrier slurry containing an organic additive

Chemically preventing copper dendrite formation and growth by spraying

Prevention of Cu dendrite formation and growth

Chemically removable Cu CMP slurry abrasive

Chemically removable Cu CMP slurry abrasive

Method of planarization of topologies in integrated circuit structures

Prevention of precipitation defects on copper interconnects during CMP by use of solutions containing organic compounds with silica adsorption and copper corrosion inhibiting properties

Point of use mixing for LI/plug tungsten polishing slurry to improve existing slurry

Ceria removal in chemical-mechanical polishing of integrated circuits

Use of Ta-capped metal line to improve formation of memory element films

SPANSION LLC

Method and structure of memory element plug with conductive Ta removed from sidewall at region of memory element film

Use of Ta-capped metal line to improve formation of memory element films

Ordered porosity to direct memory element formation

ADVANCE MICRO DEVICES INC

Graded low-k middle-etch stop layer for dual-inlaid patterning

(unassigned)

Void free oxide fill for interconnect spaces