Inventor

SHIELL JONATHAN H

US47 patents

Patents

47 patents

US5950012ASep 7, 1999

Single chip microprocessor circuits, systems, and methods for self-loading patch micro-operation codes and patch microinstruction codes

TEXAS INSTRUMENTS INC206 citations99

US5913049AJun 15, 1999

Multi-stream complex instruction set microprocessor

TEXAS INSTRUMENTS INC154 citations99

US6216219B1Apr 10, 2001

Microprocessor circuits, systems, and methods implementing a load target buffer with entries relating to prefetch desirability

TEXAS INSTRUMENTS INC172 citations98

US6209114B1Mar 27, 2001

Efficient hardware implementation of chien search polynomial reduction in reed-solomon decoding

TEXAS INSTRUMENTS INC127 citations98

US6049672AApr 11, 2000

Microprocessor with circuits, systems, and methods for operating with patch micro-operation codes and patch microinstruction codes stored in multi-purpose memory structure

TEXAS INSTRUMENTS INC140 citations98

US5951679ASep 14, 1999

Microprocessor circuits, systems, and methods for issuing successive iterations of a short backward branch loop in a single cycle

TEXAS INSTRUMENTS INC90 citations98

US5864697AJan 26, 1999

Microprocessor using combined actual and speculative branch history prediction

TEXAS INSTRUMENTS INC118 citations98

US5850543ADec 15, 1998

Microprocessor with speculative instruction pipelining storing a speculative register value within branch target buffer for use in speculatively executing instructions after a return

TEXAS INSTRUMENTS INC139 citations98

US6134634AOct 17, 2000

Data prefetching of a load target buffer for post-branch instructions based on past prediction accuracy's of branch predictions

TEXAS INSTRUMENTS INC98 citations97

US5953512ASep 14, 1999

Microprocessor circuits, systems, and methods implementing a loop and/or stride predicting load target buffer

TEXAS INSTRUMENTS INC114 citations97

US5935241AAug 10, 1999

Multiple global pattern history tables for branch prediction in a microprocessor

TEXAS INSTRUMENTS INC95 citations97

US6195735B1Feb 27, 2001

Prefetch circuity for prefetching variable size data

TEXAS INSTRUMENTS INC59 citations96

US5911057AJun 8, 1999

Superscalar microprocessor having combined register and memory renaming circuits, systems, and methods

TEXAS INSTRUMENTS INC70 citations96

US6317820B1Nov 13, 2001

Dual-mode VLIW architecture providing a software-controlled varying mix of instruction-level and task-level parallelism

TEXAS INSTRUMENTS INC78 citations95

US6038645AMar 14, 2000

Microprocessor circuits, systems, and methods using a combined writeback queue and victim cache

TEXAS INSTRUMENTS INC57 citations95

US5974440AOct 26, 1999

Microprocessor with circuits, systems, and methods for interrupt handling during virtual task operation

TEXAS INSTRUMENTS INC61 citations95

US5826084AOct 20, 1998

Microprocessor with circuits, systems, and methods for selectively bypassing external interrupts past the monitor program during virtual program operation

TEXAS INSTRUMENTS INC82 citations95

US6442667B1Aug 27, 2002

Selectively powering X Y organized memory banks

TEXAS INSTRUMENTS INC30 citations93

US6408320B1Jun 18, 2002

Instruction set architecture with versatile adder carry control

TEXAS INSTRUMENTS INC21 citations93

US6338137B1Jan 8, 2002

Data processor having memory access unit with predetermined number of instruction cycles between activation and initial data transfer

TEXAS INSTRUMENTS INC41 citations93

US6212601B1Apr 3, 2001

Microprocessor system with block move circuit disposed between cache circuits

TEXAS INSTRUMENTS INC23 citations93

US6065125AMay 16, 2000

SMM power management circuits, systems, and methods

TEXAS INSTRUMENTS INC20 citations93

US6041176AMar 21, 2000

Emulation devices utilizing state machines

TEXAS INSTRUMENTS INC35 citations93

US5961632AOct 5, 1999

Microprocessor with circuits, systems, and methods for selecting alternative pipeline instruction paths based on instruction leading codes

TEXAS INSTRUMENTS INC38 citations93

US5954812ASep 21, 1999

Apparatus for caching system management memory in a computer having a system management mode employing address translation

TEXAS INSTRUMENTS INC23 citations93

US6449692B1Sep 10, 2002

Microprocessor circuits, systems, and methods with combined on-chip pixel and non-pixel cache structure

TEXAS INSTRUMENTS INC21 citations92

US6412107B1Jun 25, 2002

Method and system of providing dynamic optimization information in a code interpretive runtime environment

TEXAS INSTRUMENTS INC64 citations92

US6178481B1Jan 23, 2001

Microprocessor circuits and systems with life spanned storage circuit for storing non-cacheable data

TEXAS INSTRUMENTS INC37 citations92

US6173410B1Jan 9, 2001

Microprocessor circuits, systems and methods for conditioning information prefetching based on resource burden

TEXAS INSTRUMENTS INC33 citations92

US6173368B1Jan 9, 2001

Class categorized storage circuit for storing non-cacheable data until receipt of a corresponding terminate signal

TEXAS INSTRUMENTS INC29 citations92

US6032225AFeb 29, 2000

Microprocessor system with burstable, non-cacheable memory access support

TEXAS INSTRUMENTS INC21 citations92

US5963721AOct 5, 1999

Microprocessor system with capability for asynchronous bus transactions

TEXAS INSTRUMENTS INC26 citations92

US5951677ASep 14, 1999

Efficient hardware implementation of euclidean array processing in reed-solomon decoding

TEXAS INSTRUMENTS INC43 citations92

US5909566AJun 1, 1999

Microprocessor circuits, systems, and methods for speculatively executing an instruction using its most recently used data while concurrently prefetching data for the instruction

TEXAS INSTRUMENTS INC23 citations92

US6138232AOct 24, 2000

Microprocessor with rate of instruction operation dependent upon interrupt source for power consumption control

TEXAS INSTRUMENTS INC45 citations91

US6085269AJul 4, 2000

Configurable expansion bus controller in a microprocessor-based system

TEXAS INSTRUMENTS INC45 citations90

US6065113AMay 16, 2000

Circuits, systems, and methods for uniquely identifying a microprocessor at the instruction set level employing one-time programmable register

TEXAS INSTRUMENTS INC37 citations89

US5799180AAug 25, 1998

Microprocessor circuits, systems, and methods passing intermediate instructions between a short forward conditional branch instruction and target instruction through pipeline, then suppressing results if branch taken

TEXAS INSTRUMENTS INC45 citations87

US6064254AMay 16, 2000

High speed integrated circuit interconnection having proximally located active converter

TEXAS INSTRUMENTS INC9 citations74

US5815697ASep 29, 1998

Circuits, systems, and methods for reducing microprogram memory power for multiway branching

TEXAS INSTRUMENTS INC10 citations74

US6401212B1Jun 4, 2002

Microprocessor circuits, systems, and methods for conditioning information prefetching based on resource burden

TEXAS INSTRUMENTS INC8 citations73

US5958046ASep 28, 1999

Microprocessor with reduced microcode space requirements due to improved branch target microaddress circuits, systems, and methods

TEXAS INSTRUMENTS INC9 citations73

US6170053B1Jan 2, 2001

Microprocessor with circuits, systems and methods for responding to branch instructions based on history of prediction accuracy

TEXAS INSTRUMENTS INC11 citations72

US5903742AMay 11, 1999

Method and circuit for redefining bits in a control register

TEXAS INSTRUMENTS INC1 citations52

SHIELL JONATHAN H

Patents

Single chip microprocessor circuits, systems, and methods for self-loading patch micro-operation codes and patch microinstruction codes

Multi-stream complex instruction set microprocessor

Microprocessor circuits, systems, and methods implementing a load target buffer with entries relating to prefetch desirability

Efficient hardware implementation of chien search polynomial reduction in reed-solomon decoding

Microprocessor with circuits, systems, and methods for operating with patch micro-operation codes and patch microinstruction codes stored in multi-purpose memory structure

Microprocessor circuits, systems, and methods for issuing successive iterations of a short backward branch loop in a single cycle

Microprocessor using combined actual and speculative branch history prediction

Microprocessor with speculative instruction pipelining storing a speculative register value within branch target buffer for use in speculatively executing instructions after a return

Method and apparatus for preemptive cache write-back

Combined branch prediction and cache prefetch in a microprocessor

Dynamically loadable pattern history tables in a multi-task microprocessor

Data prefetching of a load target buffer for post-branch instructions based on past prediction accuracy&#39;s of branch predictions

Microprocessor circuits, systems, and methods implementing a loop and/or stride predicting load target buffer

Multiple global pattern history tables for branch prediction in a microprocessor

Prefetch circuity for prefetching variable size data

Superscalar microprocessor having combined register and memory renaming circuits, systems, and methods

Dual-mode VLIW architecture providing a software-controlled varying mix of instruction-level and task-level parallelism

Microprocessor circuits, systems, and methods using a combined writeback queue and victim cache

Microprocessor with circuits, systems, and methods for interrupt handling during virtual task operation

Microprocessor with circuits, systems, and methods for selectively bypassing external interrupts past the monitor program during virtual program operation

Selectively powering X Y organized memory banks

Instruction set architecture with versatile adder carry control

Data processor having memory access unit with predetermined number of instruction cycles between activation and initial data transfer

Microprocessor system with block move circuit disposed between cache circuits

SMM power management circuits, systems, and methods

Emulation devices utilizing state machines

Microprocessor with circuits, systems, and methods for selecting alternative pipeline instruction paths based on instruction leading codes

Apparatus for caching system management memory in a computer having a system management mode employing address translation

Microprocessor circuits, systems, and methods with combined on-chip pixel and non-pixel cache structure

Method and system of providing dynamic optimization information in a code interpretive runtime environment

Microprocessor circuits and systems with life spanned storage circuit for storing non-cacheable data

Microprocessor circuits, systems and methods for conditioning information prefetching based on resource burden

Class categorized storage circuit for storing non-cacheable data until receipt of a corresponding terminate signal

Microprocessor system with burstable, non-cacheable memory access support

Microprocessor system with capability for asynchronous bus transactions

Efficient hardware implementation of euclidean array processing in reed-solomon decoding

Microprocessor circuits, systems, and methods for speculatively executing an instruction using its most recently used data while concurrently prefetching data for the instruction

Microprocessor with rate of instruction operation dependent upon interrupt source for power consumption control

Configurable expansion bus controller in a microprocessor-based system

Circuits, systems, and methods for uniquely identifying a microprocessor at the instruction set level employing one-time programmable register

Microprocessor circuits, systems, and methods passing intermediate instructions between a short forward conditional branch instruction and target instruction through pipeline, then suppressing results if branch taken

High speed integrated circuit interconnection having proximally located active converter

Circuits, systems, and methods for reducing microprogram memory power for multiway branching

Microprocessor circuits, systems, and methods for conditioning information prefetching based on resource burden

Microprocessor with reduced microcode space requirements due to improved branch target microaddress circuits, systems, and methods

Microprocessor with circuits, systems and methods for responding to branch instructions based on history of prediction accuracy

Method and circuit for redefining bits in a control register

Data prefetching of a load target buffer for post-branch instructions based on past prediction accuracy's of branch predictions