Inventor

CHANG CHUNG-LONG

TW60 patents

⚠️ This page may combine multiple inventors who share the name “CHANG CHUNG-LONG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CHANG CHUNG-LONG

TAIWAN SEMICONDUCTOR MFG

Copper chemical-mechanical-polishing (CMP) dishing

Methods to improve copper-fluorinated silica glass interconnects

Readable alignment mark structure formed using enhanced chemical mechanical polishing

Method of fabricating a readable alignment mark structure using enhanced chemical mechanical polishing

Process for polishing the top surface of a polysilicon gate

Process flow to optimize profile of ultra small size photo resist free contact

Chemical mechanical polishing of polysilicon plug using a silicon nitride stop layer

Process to improve adhesion of HSQ to underlying materials

Integrated capacitor

Metal-over-metal devices and the method for manufacturing same

High fMAX deep submicron MOSFET

Self-aligned process for a stacked gate RF MOSFET device

Multi-step chemical mechanical polish (CMP) planarizing method for forming patterned planarized aperture fill layer

Alignment method for used in chemical mechanical polishing process

Method for CMP cleaning improvement

Device and method for providing shielding in radio frequency integrated circuits to reduce noise coupling

Antennas integrated in semiconductor chips

Capacitor pairs with improved mismatch performance

Method of CMP of polysilicon

Chemical-mechanical polish method using an undoped silicon glass stop layer for polishing BPSG

Method to form self-aligned contacts with polysilicon plugs

Etchback method for forming microelectronic layer with enhanced surface smoothness

MOM capacitors integrated with air-gaps

Capacitors integrated with metal gate formation

Capacitor device with vertically arranged capacitor regions of various kinds

Prevention of die loss to chemical mechanical polishing

Capacitor pairs with improved mismatch performance

Interdigitated capacitor and method for fabrication thereof

Self-aligned process for a stacked gate RF MOSFET device

Method for smoothing polysilicon gate structures in CMOS devices

Method of CMP of polysilicon

Reduction of surface contamination in post-CMP cleaning

Method for stud pull test for film formed on semiconductor device

Layout for capacitor pair with high capacitance matching

High fMAX deep submicron MOSFET

Chemical mechanical polishing of polysilicon plug using a silicon nitride stop layer

Method to solve alignment mark blinded issues and a technology for application of semiconductor etching at a tiny area

Micro-etching method to replicate alignment marks for semiconductor wafer photolithography

TAIWAN SEMICONDUCTOR MFG CO LTD

Handle wafer for high resistivity trap-rich SOI

Multi-terminal inductor for integrated circuit

Semiconductor structure with ultra thick metal and manufacturing method thereof

Multi-terminal inductor for integrated circuit

Integrated circuit and manufacturing method thereof

Semiconductor structure with ultra thick metal and manufacturing method thereof

Semiconductor structure with ultra thick metal and manufacturing method thereof

Integrated circuit

CHANG CHUNG-LONG

Semiconductor device structure for reducing mismatch effects

Capacitors integrated with metal gate formation

Contact structure for reducing gate resistance and method of making the same

CHEN YUEH-YOU

Interdigitated capacitive structure for an integrated circuit