Inventor

ANDERSON TIMOTHY D

US122 patents

⚠️ This page may combine multiple inventors who share the name “ANDERSON TIMOTHY D”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

ANDERSON TIMOTHY D

TEXAS INSTRUMENTS INC

Highly integrated scalable, flexible DSP megamodule architecture

Highly integrated scalable, flexible DSP megamodule architecture

Microprocessor with non-aligned memory access

Microprocessor circuits, systems, and methods for issuing successive iterations of a short backward branch loop in a single cycle

Coherent cache system with optional acknowledgement for out-of-order coherence transaction completion

Unified memory system architecture including cache and directly addressable static random access memory

Pipelined microprocessor with efficient self-modifying code detection and handling

Streaming engine with stream metadata saving for context switching

Multi-master cache coherent speculation aware memory controller with advanced arbitration, virtualization and EDC

Highly integrated scalable, flexible DSP megamodule architecture

Programmable built in self test of memory

Programmer initiated cache block operations

Method and apparatus for operating one or more caches in conjunction with direct memory access controller

Multilevel cache system coherence with memory selectively configured as cache or direct access memory and direct memory access

Unified multilevel memory system architecture which supports both cache and addressable SRAM

Automated method for testing cache

Secure master and secure guest endpoint security firewall

Pipeline protection for CPUs with save and restore of intermediate results

Nested loop control

Streaming engine with deferred exception reporting

Secure master and secure guest endpoint security firewall

Faster and more efficient different precision sum of absolute differences for dynamically configurable block searches for motion estimation

Memory error detection reporting

Exit history based branch prediction

Instruction-programmable processor with instruction loop cache

Microprocessor with branch-decrement instruction that provides a target and conditionally modifies a test register if the register meets a condition

Four state token passing alignment fault state circuit for microprocessor address misalignment fault generation having combined read/write port

Highly integrated scalable, flexible DSP megamodule architecture

Pipeline protection for CPUs with save and restore of intermediate results

Mechanism for interrupting and resuming execution on an unprotected pipeline processor

Streaming engine with deferred exception reporting

Variable latency instructions

Entering protected pipeline mode without annulling pending instructions

Mechanism for interrupting and resuming execution on an unprotected pipeline processor

Multicore bus architecture with non-blocking high performance transaction credit system

Streaming engine with deferred exception reporting

Streaming engine with early and late address and loop count registers to track architectural state

Multicore bus architecture with non-blocking high performance transaction credit system

Protection of memories, datapath and pipeline registers, and other storage elements by distributed delayed detection and correction of soft errors

CHIRCA KAI

Multilayer arbitration for access to multiple destinations

Speculation-aware memory controller arbiter

Memory controller with automatic error detection and correction

ANDERSON TIMOTHY D

Refrigerated merchandiser with shelf air discharge

Variable line size prefetcher for multiple memory requestors

Predictive sequential prefetching for data caching

HUSSMANN CORP

Multi-zone circuiting for a plate-fin and continuous tube heat exchanger

Merchandiser with airflow divider

ZBICIAK JOSEPH R M

Flexible memory protection and translation unit

RAHMAN MUJIBUR

Family of multiplexer/flip-flops with enhanced testability

ATTEY JOEL

Low heat transfer magnetic shelf attachment