Inventor · disambiguated record
David E. Freker
Also filed as: FREKER DAVID · FREKER DAVID E
13 granted patents·4 pending applications·720 citations·filing 1996–2007
94Inventor score
Top patents by PatentIndex Score
17 records- 0196US5835435AMethod and apparatus for dynamically placing portions of a memory in a reduced power consumtion stateINTEL CORP·Filed 1997·Granted Nov 10, 1998·159 cites·22 claims
- 0293US6141283AMethod and apparatus for dynamically placing portions of a memory in a reduced power consumption stateINTEL CORP·Filed 1999·Granted Oct 31, 2000·120 cites·10 claims
- 0389US5987628AMethod and apparatus for automatically correcting errors detected in a memory subsystemINTEL CORP·Filed 1997·Granted Nov 16, 1999·155 cites·25 claims
- 0484US7047384B2Method and apparatus for dynamic timing of memory interface signalsINTEL CORP·Filed 2002·Granted May 16, 2006·45 cites·20 claims
- 0583US7269754B2Method and apparatus for flexible and programmable clock crossing control with dynamic compensationINTEL CORP·Filed 2002·Granted Sep 11, 2007·40 cites·19 claims
- 0677US6041016AOptimizing page size in mixed memory array using address multiplexingINTEL CORP·Filed 1998·Granted Mar 21, 2000·38 cites·15 claims
- 0773US6408398B1Method and apparatus for detecting time domains on a communication channelINTEL CORP·Filed 1999·Granted Jun 18, 2002·61 cites·25 claims
- 0866US6564335B1Cross chip transfer mechanism for a memory repeater chip in a Dram memory systemINTEL CORP·Filed 2000·Granted May 13, 2003·12 cites·24 claims
- 0966US6181619B1Selective automatic precharge of dynamic random access memory banksINTEL CORP·Filed 1998·Granted Jan 30, 2001·23 cites·20 claims
- 1061US7230627B2Optimized memory addressingINTEL CORP·Filed 2004·Granted Jun 12, 2007·6 cites·25 claims
- 1161US5678009AMethod and apparatus providing fast access to a shared resource on a computer busINTEL CORP·Filed 1996·Granted Oct 14, 1997·46 cites·24 claims
- 1259US7612780B2Optimized memory addressingINTEL CORP·Filed 2007·Granted Nov 3, 2009·1 cites·14 claims
- 1344US2005190193A1Apparatus and a method to adjust signal timing on a memory interfaceFiled 2004·Application pending·0 cites
- 1442US6442645B1Pre-decode conditional command generation for reduced SDRAM cycle latencyINTEL CORP·Filed 1998·Granted Aug 27, 2002·14 cites·16 claims
- 1540US2005198542A1Method and apparatus for a variable memory enable deassertion wait timeFiled 2004·Application pending·0 cites
- 1639US2006245473A1Integrating receivers for source synchronous protocolCHENG ROGER K·Filed 2005·Application pending·0 cites
- 1739US2004003194A1Method and apparatus for adjusting DRAM signal timingsFiled 2002·Application pending·0 cites
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