Inventor · disambiguated record
Holger Wetter
Also filed as: WETTER HOLGER
16 granted patents·2 pending applications·44 citations·filing 1997–2021
89Inventor score
Top patents by PatentIndex Score
18 records- 0164US8560983B2Incorporating synthesized netlists as subcomponents in a hierarchical custom designBRANDT UWE·Filed 2011·Granted Oct 15, 2013·2 cites·21 claims
- 0260US7873687B2Method for calculating a result of a division with a floating point unit with fused multiply-addIBM·Filed 2006·Granted Jan 18, 2011·2 cites·5 claims
- 0359US10579773B2Layouting of interconnect lines in integrated circuitsIBM·Filed 2018·Granted Mar 3, 2020·0 cites·4 claims
- 0458US10417377B2Layouting of interconnect lines in integrated circuitsIBM·Filed 2018·Granted Sep 17, 2019·0 cites·12 claims
- 0557US11527283B2Single ended bitline current sense amplifiersIBM·Filed 2021·Granted Dec 13, 2022·0 cites·25 claims
- 0656US9761304B1Write-bitline control in multicore SRAM arraysIBM·Filed 2016·Granted Sep 12, 2017·1 cites·17 claims
- 0754US10013521B2Layouting of interconnect lines in integrated circuitsIBM·Filed 2015·Granted Jul 3, 2018·0 cites·6 claims
- 0850US7913132B2System and method for scanning sequential logic elementsIBM·Filed 2008·Granted Mar 22, 2011·1 cites·14 claims
- 0949US11664068B2Single ended current mode sense amplifier with feedback inverterIBM·Filed 2021·Granted May 30, 2023·0 cites·17 claims
- 1044US9922154B2Enabling an incremental sign-off process using design dataIBM·Filed 2016·Granted Mar 20, 2018·0 cites·20 claims
- 1144US2004249877A1Fast integer division with minimum number of iterations in substraction-based hardware divide processorIBM·Filed 2004·Application pending·0 cites
- 1243US8332453B2Shifter with all-one and all-zero detection using a portion of partially shifted vector and shift amount in parallel to generated shifted resultBOERSMA MAARTEN·Filed 2008·Granted Dec 11, 2012·0 cites·15 claims
- 1343US6292819B1Binary and decimal adder unitIBM·Filed 1999·Granted Sep 18, 2001·19 cites·20 claims
- 1442US2006031279A1Highly parallel structure for fast multi cycle binary and decimal adder unitIBM·Filed 2005·Application pending·0 cites
- 1540US8286115B2Fast routing of custom macrosWETTER HOLGER·Filed 2008·Granted Oct 9, 2012·0 cites·13 claims
- 1640US5928319ACombined binary/decimal adder unitIBM·Filed 1997·Granted Jul 27, 1999·13 cites·12 claims
- 1733US5944772ACombined adder and logic unitIBM·Filed 1997·Granted Aug 31, 1999·6 cites·18 claims
- 1830US9837143B1NAND-based write driver for SRAMIBM·Filed 2016·Granted Dec 5, 2017·0 cites·6 claims
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →