Inventor
RAHIM SOLAIMAN
US19 patents
⚠️ This page may combine multiple inventors who share the name “RAHIM SOLAIMAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
SYNOPSYS INC
12 patentsUS10621296B1Apr 14, 2020
Generating SAIF efficiently from hardware platforms
SYNOPSYS INC2 citations67
US12001317B2Jun 4, 2024
Waveform based reconstruction for emulation
SYNOPSYS INC0 citations58
US11726899B2Aug 15, 2023
Waveform based reconstruction for emulation
SYNOPSYS INC0 citations58
US11200149B2Dec 14, 2021
Waveform based reconstruction for emulation
SYNOPSYS INC0 citations58
US12124780B2Oct 22, 2024
Power estimation using input vectors and deep recurrent neural networks
SYNOPSYS INC1 citations57
US11651129B2May 16, 2023
Selecting a subset of training data from a data pool for a power prediction model
SYNOPSYS INC1 citations57
US12093620B1Sep 17, 2024
Multi-cycle power analysis of integrated circuit designs
SYNOPSYS INC0 citations55
US11842132B1Dec 12, 2023
Multi-cycle power analysis of integrated circuit designs
SYNOPSYS INC1 citations55
US12254255B1Mar 18, 2025
Glitch identification and power analysis using simulation vectors
SYNOPSYS INC0 citations53
US11651131B2May 16, 2023
Glitch source identification and ranking
SYNOPSYS INC0 citations49
US12001768B1Jun 4, 2024
Enhanced glitch estimation in vectorless power analysis
SYNOPSYS INC0 citations41
US9405872B2Aug 2, 2016
System and method for reducing power of a circuit using critical signal analysis
SYNOPSYS INC0 citations36
ATRENTA INC
6 patentsUS7650581B2Jan 19, 2010
Method for modeling and verifying timing exceptions
ATRENTA INC11 citations83
US8656326B1Feb 18, 2014
Sequential clock gating using net activity and XOR technique on semiconductor designs including already gated pipeline design
ATRENTA INC7 citations82
US8042085B2Oct 18, 2011
Method for compaction of timing exception paths
ATRENTA INC5 citations57
US8677295B1Mar 18, 2014
Sequential clock gating using net activity and xor technique on semiconductor designs including already gated pipeline design
ATRENTA INC1 citations50
US8984469B2Mar 17, 2015
System and method for strengthening of a circuit element to reduce an integrated circuit's power consumption
ATRENTA INC1 citations48
US8635578B1Jan 21, 2014
System and method for strengthening of a circuit element to reduce an integrated circuit's power consumption
ATRENTA INC1 citations48