Inventor

KELLER JAMES B

US113 patents

⚠️ This page may combine multiple inventors who share the name “KELLER JAMES B”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

KELLER JAMES B

ADVANCED MICRO DEVICES INC

Maintaining cache coherency during a memory read operation in a multiprocessing computer system

Implementing locks in a distributed processing system

Circuit and method for maintaining order of memory access requests initiated by devices coupled to a multiprocessor system

Computer system implementing a system and method for tracking the progress of posted write transactions

Flexible probe/probe response routing for maintaining coherency

Double prefix overrides to provide 16-bit operand size in a 32/64 operating mode

Scheduler capable of issuing and reissuing dependency chains

Circuit and method for maintaining order of memory access requests initiated by devices in a multiprocessor system

Messaging scheme to maintain cache coherency and conserve system memory bandwidth during a memory read operation in a multiprocessing computer system

Pipeline elements which verify predecode information

System and method of increasing bandwidth for issuing ordered transactions into a distributed communication system

Store load forward predictor training

Cache which provides partial tags from non-predicted ways to direct search if way prediction misses

Store to load forward predictor training using delta tag

Virtual channels and corresponding buffer allocations for deadlock-free computer system operation

Method and apparatus for using a control signal on a packet based communication link

Conserving system memory bandwidth during a memory read operation in a multiprocessing computer system

Determination of execution resource allocation based on concurrently executable misaligned memory operations

Computer system implementing a system and method for ordering input/output (IO) memory operations within a coherent portion thereof

Computer system implementing flush operation

Computer system implementing system and method for ordering write operations and maintaining memory coherency

Physical rename register for efficiently storing floating point, integer, condition code, and multimedia values

Conversation of distributed memory bandwidth in multiprocessor system with cache coherency by transmitting cancel subsequent to victim write

Memory cancel response optionally cancelling memory controller&#39;s providing of data in response to a read operation

Physical rename register for efficiently storing floating point, integer, condition code, and multimedia values

Implementing locks in a distributed processing system

Store load forward predictor untraining

Scheduler which retries load/store hit situations

Scheduler which discovers non-speculative nature of an instruction after issuing and reissues the instruction

Circuit and method for selectively stalling interrupt requests initiated by devices coupled to a multiprocessor system

BROADCOM CORP

Memory controller with programmable configuration

Memory controller with programmable configuration

Adaptive retry mechanism

Programmably disabling one or more cache entries

System having interfaces and switch that separates coherent and packet traffic

APPLE INC

Trust zone support in system on a chip having security enclave processor

Combined transparent/non-transparent cache

Non-blocking address switch with shallow per agent queues

L1 cache flush when processor is entering low power mode

WANG JAMES

Cache implementing multiple replacement policies

Combined transparent/non-transparent cache

Block-based non-transparent cache

COMPAQ INFORMATION TECHNOLOGIE

Method and apparatus for performing speculative memory fills into a microprocessor

Method and apparatus for developing multiprocessor cache control protocols by presenting a clean victim signal to an external system

Data cache having store queue bypass for out-of-order instruction execution and method for same

ALPHA PROCESSOR INC

System and method for implementing a separate virtual channel for posted requests in a multiprocessor computer system

COMPAQ COMPUTER CORP

Method and apparatus for minimizing dcache index match aliasing using hashing in synonym/subset processing

PA SEMI INC

Non-blocking address switch with shallow per agent queues

API NETWORKS INC

System and method of maintaining coherency in a distributed communication system

HEWLETT PACKARD DEVELOPMENT CO

High speed bus system that incorporates uni-directional point-to-point buses

Memory cancel response optionally cancelling memory controller's providing of data in response to a read operation