Inventor
SCHAKEL KEITH R
US48 patents
⚠️ This page may combine multiple inventors who share the name “SCHAKEL KEITH R”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
RAJAN SURESH NATARAJAN
21 patentsUS8745321B2Jun 3, 2014
Simulating a memory standard
RAJAN SURESH NATARAJAN68 citations98
US8671244B2Mar 11, 2014
Simulating a memory standard
RAJAN SURESH NATARAJAN66 citations98
US8667312B2Mar 4, 2014
Performing power management operations
RAJAN SURESH NATARAJAN76 citations98
US8601204B2Dec 3, 2013
Simulating a refresh operation latency
RAJAN SURESH NATARAJAN70 citations98
US8595419B2Nov 26, 2013
Memory apparatus operable to perform a power-saving operation
RAJAN SURESH NATARAJAN68 citations98
US8566556B2Oct 22, 2013
Memory module with memory stack and interface with enhanced capabilities
RAJAN SURESH NATARAJAN68 citations98
US8340953B2Dec 25, 2012
Memory circuit simulation with power saving capabilities
RAJAN SURESH NATARAJAN75 citations98
US8280714B2Oct 2, 2012
Memory circuit simulation system and method with refresh capabilities
RAJAN SURESH NATARAJAN66 citations98
US8244971B2Aug 14, 2012
Memory circuit system and method
RAJAN SURESH NATARAJAN86 citations98
US8209479B2Jun 26, 2012
Memory circuit system and method
RAJAN SURESH NATARAJAN85 citations98
US8181048B2May 15, 2012
Performing power management operations
RAJAN SURESH NATARAJAN67 citations98
US8154935B2Apr 10, 2012
Delaying a signal communicated from a system to at least one of a plurality of memory circuits
RAJAN SURESH NATARAJAN69 citations98
US8112266B2Feb 7, 2012
Apparatus for simulating an aspect of a memory circuit
RAJAN SURESH NATARAJAN70 citations98
US8090897B2Jan 3, 2012
System and method for simulating an aspect of a memory circuit
RAJAN SURESH NATARAJAN73 citations98
US8868829B2Oct 21, 2014
Memory circuit system and method
RAJAN SURESH NATARAJAN17 citations93
US8949519B2Feb 3, 2015
Simulating a memory circuit
RAJAN SURESH NATARAJAN11 citations84
US8797779B2Aug 5, 2014
Memory module with memory stack and interface with enhanced capabilites
RAJAN SURESH NATARAJAN12 citations84
US9542353B2Jan 10, 2017
System and method for reducing command scheduling constraints of memory circuits
RAJAN SURESH NATARAJAN5 citations73
US9542352B2Jan 10, 2017
System and method for reducing command scheduling constraints of memory circuits
RAJAN SURESH NATARAJAN2 citations73
US9632929B2Apr 25, 2017
Translating an address associated with a command communicated between a system and memory circuits
RAJAN SURESH NATARAJAN0 citations52
US9047976B2Jun 2, 2015
Combined signal delay and power saving for use with a plurality of memory circuits
RAJAN SURESH NATARAJAN0 citations52
GOOGLE INC
8 patentsUS8019589B2Sep 13, 2011
Memory apparatus operable to perform a power-saving operation
GOOGLE INC80 citations99
US7761724B2Jul 20, 2010
Interface circuit system and method for performing power management operations in conjunction with only a portion of a memory circuit
GOOGLE INC138 citations99
US7730338B2Jun 1, 2010
Interface circuit system and method for autonomously performing power management operations in conjunction with a plurality of memory circuits
GOOGLE INC135 citations99
US7724589B2May 25, 2010
System and method for delaying a signal communicated from a system to at least one of a plurality of memory circuits
GOOGLE INC140 citations99
US8359187B2Jan 22, 2013
Simulating a different number of memory circuit devices
GOOGLE INC66 citations98
US8041881B2Oct 18, 2011
Memory device with emulated characteristics
GOOGLE INC75 citations98
US9171585B2Oct 27, 2015
Configurable memory circuit system and method
GOOGLE INC65 citations96
US9507739B2Nov 29, 2016
Configurable memory circuit system and method
GOOGLE INC3 citations73
METARAM INC
7 patentsUS7609567B2Oct 27, 2009
System and method for simulating an aspect of a memory circuit
METARAM INC136 citations99
US7590796B2Sep 15, 2009
System and method for power management in memory systems
METARAM INC141 citations99
US7581127B2Aug 25, 2009
Interface circuit system and method for performing power saving operations during a command-related latency
METARAM INC137 citations99
US7472220B2Dec 30, 2008
Interface circuit system and method for performing power management operations utilizing power management signals
METARAM INC152 citations99
US7392338B2Jun 24, 2008
Interface circuit system and method for autonomously performing power management operations in conjunction with a plurality of memory circuits
METARAM INC137 citations99
US7386656B2Jun 10, 2008
Interface circuit system and method for performing power management operations in conjunction with only a portion of a memory circuit
METARAM INC147 citations99
US7580312B2Aug 25, 2009
Power saving system and method for use with a plurality of memory circuits
METARAM INC134 citations98
ADVANCED MICRO DEVICES INC
6 patentsUS6502185B1Dec 31, 2002
Pipeline elements which verify predecode information
ADVANCED MICRO DEVICES INC92 citations97
US6687789B1Feb 3, 2004
Cache which provides partial tags from non-predicted ways to direct search if way prediction misses
ADVANCED MICRO DEVICES INC53 citations96
US6622237B1Sep 16, 2003
Store to load forward predictor training using delta tag
ADVANCED MICRO DEVICES INC59 citations96
US6647490B2Nov 11, 2003
Training line predictor for branch targets
ADVANCED MICRO DEVICES INC13 citations84
US6546478B1Apr 8, 2003
Line predictor entry with location pointers and control information for corresponding instructions in a cache line
ADVANCED MICRO DEVICES INC15 citations84
US6636959B1Oct 21, 2003
Predictor miss decoder updating line predictor storing instruction fetch address and alignment information upon instruction decode termination condition
ADVANCED MICRO DEVICES INC12 citations73