Inventor
MASTRONARDE JOSH
US10 patents
Patents
10 patentsUS10803548B2Oct 13, 2020
Disaggregation of SOC architecture
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US12079155B2Sep 3, 2024
Graphics processor operation scheduling for deterministic latency
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US11756150B2Sep 12, 2023
Disaggregation of system-on-chip (SOC) architecture
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US11410266B2Aug 9, 2022
Disaggregation of System-On-Chip (SOC) architecture
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US11386521B2Jul 12, 2022
Enabling product SKUS based on chiplet configurations
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US10909652B2Feb 2, 2021
Enabling product SKUs based on chiplet configurations
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US12141890B2Nov 12, 2024
Enabling product SKUs based on chiplet configurations
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US12112398B2Oct 8, 2024
Disaggregation of system-on-chip (SOC) architecture
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US12056789B2Aug 6, 2024
Disaggregation of system-on-chip (SOC) architecture
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US11763416B2Sep 19, 2023
Disaggregation of system-on-chip (SOC) architecture
INTEL CORP0 citations62