Inventor
RAJWANI IQBAL
US19 patents
Patents
19 patentsUS10803548B2Oct 13, 2020
Disaggregation of SOC architecture
INTEL CORP32 citations97
US11756150B2Sep 12, 2023
Disaggregation of system-on-chip (SOC) architecture
INTEL CORP5 citations85
US11410266B2Aug 9, 2022
Disaggregation of System-On-Chip (SOC) architecture
INTEL CORP6 citations85
US7130236B2Oct 31, 2006
Low power delay controlled zero sensitive sense amplifier
INTEL CORP17 citations83
US9355694B2May 31, 2016
Assist circuit for memory
INTEL CORP10 citations82
US11386521B2Jul 12, 2022
Enabling product SKUS based on chiplet configurations
INTEL CORP2 citations72
US10909652B2Feb 2, 2021
Enabling product SKUs based on chiplet configurations
INTEL CORP4 citations72
US10747286B2Aug 18, 2020
Dynamic power budget allocation in multi-processor system
INTEL CORP4 citations72
US10491217B2Nov 26, 2019
Low-power clock gate circuit
INTEL CORP5 citations72
US12141890B2Nov 12, 2024
Enabling product SKUs based on chiplet configurations
INTEL CORP0 citations62
US12112398B2Oct 8, 2024
Disaggregation of system-on-chip (SOC) architecture
INTEL CORP0 citations62
US12056789B2Aug 6, 2024
Disaggregation of system-on-chip (SOC) architecture
INTEL CORP0 citations62
US11874715B2Jan 16, 2024
Dynamic power budget allocation in multi-processor system
INTEL CORP0 citations62
US11763416B2Sep 19, 2023
Disaggregation of system-on-chip (SOC) architecture
INTEL CORP0 citations62
US11493974B2Nov 8, 2022
Dynamic power budget allocation in multi-processor system
INTEL CORP0 citations62
US10333379B2Jun 25, 2019
Power switching circuitry including power-up control
INTEL CORP1 citations56
US12367926B2Jul 22, 2025
Apparatus and method to optimize sense-amp enable pulse-width in SRAM arrays
INTEL CORP0 citations54
US11908542B2Feb 20, 2024
Energy efficient memory array with optimized burst read and write data access
INTEL CORP0 citations52
US9685208B2Jun 20, 2017
Assist circuit for memory
INTEL CORP0 citations50