Inventor
MOSS ROBERT W
US30 patents
⚠️ This page may combine multiple inventors who share the name “MOSS ROBERT W”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
LSI LOGIC CORP
21 patentsUS6741096B2May 25, 2004
Structure and methods for measurement of arbitration performance
LSI LOGIC CORP71 citations98
US6646929B1Nov 11, 2003
Methods and structure for read data synchronization with minimal latency
LSI LOGIC CORP219 citations98
US6600681B1Jul 29, 2003
Method and apparatus for calibrating DQS qualification in a memory controller
LSI LOGIC CORP134 citations97
US6366530B1Apr 2, 2002
Synchronizing data operations across a synchronization boundary between different clock domains using two-hot encoding
LSI LOGIC CORP105 citations97
US6509762B1Jan 21, 2003
Method and apparatus for measuring the phase of captured read data
LSI LOGIC CORP43 citations96
US6496043B1Dec 17, 2002
Method and apparatus for measuring the phase of captured read data
LSI LOGIC CORP55 citations96
US7174401B2Feb 6, 2007
Look ahead split release for a data bus
LSI LOGIC CORP25 citations92
US6985985B2Jan 10, 2006
Methods and structure for dynamic modifications to arbitration for a shared resource
LSI LOGIC CORP31 citations92
US6917561B2Jul 12, 2005
Memory controller and method of aligning write data to a memory device
LSI LOGIC CORP23 citations92
US6907491B2Jun 14, 2005
Methods and structure for state preservation to improve fairness in bus arbitration
LSI LOGIC CORP26 citations92
US6327207B1Dec 4, 2001
Synchronizing data operations across a synchronization boundary between different clock domains using two-hot encoding
LSI LOGIC CORP40 citations92
US6999542B1Feb 14, 2006
Data ready indicator between different clock domains
LSI LOGIC CORP18 citations84
US6892289B2May 10, 2005
Methods and structure for using a memory model for efficient arbitration
LSI LOGIC CORP13 citations84
US6807593B1Oct 19, 2004
Enhanced bus architecture for posted read operation between masters and slaves
LSI LOGIC CORP16 citations83
US7013356B2Mar 14, 2006
Methods and structure for preserving lock signals on multiple buses coupled to a multiported device
LSI LOGIC CORP9 citations74
US7065683B1Jun 20, 2006
Long path at-speed testing
LSI LOGIC CORP7 citations72
US6948019B2Sep 20, 2005
Apparatus for arbitrating non-queued split master devices on a data bus
LSI LOGIC CORP7 citations72
US6910087B2Jun 21, 2005
Dynamic command buffer for a slave device on a data bus
LSI LOGIC CORP5 citations62
US6798186B2Sep 28, 2004
Physical linearity test for integrated circuit delay lines
LSI LOGIC CORP5 citations62
US6938113B2Aug 30, 2005
Apparatus for flushing slave transactions from resetting masters of a data bus
LSI LOGIC CORP4 citations61
US6725306B2Apr 20, 2004
DEBUG mode for a data bus
LSI LOGIC CORP3 citations61
SEAGATE TECHNOLOGY LLC
7 patentsUS10142304B2Nov 27, 2018
Encryption key shredding to protect non-persistent data
SEAGATE TECHNOLOGY LLC6 citations82
US11210406B2Dec 28, 2021
Encrypting system level data structures
SEAGATE TECHNOLOGY LLC2 citations71
US10289305B2May 14, 2019
Enhanced read recovery based on write time information
SEAGATE TECHNOLOGY LLC1 citations61
US10715509B2Jul 14, 2020
Encryption key shredding to protect non-persistent data
SEAGATE TECHNOLOGY LLC1 citations60
US9977597B2May 22, 2018
Enhanced read recovery based on write time information
SEAGATE TECHNOLOGY LLC0 citations50
US10270586B2Apr 23, 2019
Random time generated interrupts in a cryptographic hardware pipeline circuit
SEAGATE TECHNOLOGY LLC0 citations42
US10211976B2Feb 19, 2019
Hash authenticated data
SEAGATE TECHNOLOGY LLC0 citations39